Customer uses EPWM2_CMPB as INT for a CLA task. EPMW2_CMP is the falling edge of one of the PWM outputs.When the CLA task is started, a GPIO is set for debugging. From PWM falling edge to GPIO high, there is a constant delay of about 240-250ns which is pretty much.
What is the delay when an interrupt is setup to trigger a CLA task?
Is there a ‘fixed’ delay time between INT trigger and the 1st instruction of the CLA task?
Regards,
Bernd
