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Delta Sigma Modulator (AMC1304) interface with TMS320F28377D

Other Parts Discussed in Thread: TMS320F28377D, AMC1304M25


I am using AMC1304M25 modulator with Delfino uC TMS320F28377D for measuring the high voltage inverter current and I have following queries.

1) I generated a 10MHz Clock using ePWM peripheral of uC (only Time Base, Counter Compare and Action Qualifier submodules are used) but it seems creepy. I am afraid if my code configuration is problematic (I tested it with different combinations of TBPRD counter and TBCLK) or if I am missing something? In any case, would this clock be fine for delta sigma modulator ? or how can I improve it? (Attached Clock signal and code configuration)

2) What should be the software settings for a resgister values of PWM11.CMPC and PWM11.CMPD which are used to synchronise SDFM module internally? What is the relation of these compare register values with PWM CLK?

your remarks are highly appreciated. Thanks.

Best Regards,


  • Hi Inam,

    Answer for your first question : Use the PWM Chopper Submodule.

  • Inan,

    1) The ringing effect that you see on PWM signal look normal. It is due to gibbs phenomenon. There is lot of material available on internet about this effect.
    This will not affect the functionality of SDFM.

    2) PWM11.CMPC and PWM11.CMPD can be configured to provide SDSYNC event from PWM to SDFM. This allows the user to synchronize your SDFM results with respect to PWM.

    When you want to synchronize SDFM with respect to PWM depends upon your application.



  • hello Prakash,

    I am quite new in this field but i gave a short glimpse to PWM chopper module. I dont think it can solve the ringing problem. It is rather targeted for other transformer based drivers to avoid saturation of gate drivers. If you have any sample code shapping PWM chopper module. You are welcome to share with us.



  • Hi,

    I have configured the Sys Clk as 160MHz and ePWM CLk as 80MHz.

    void configEPWM4()
       // Setup TBCLK
       EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
       EPwm4Regs.TBPRD = EPWM4_TIMER_TBPRD;       // Set timer period : 800
       EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE;    // Disable phase loading
       EPwm4Regs.TBPHS.bit.TBPHS = 0x0000;        // Phase is 0
       EPwm4Regs.TBCTR = 0x0000;                  // Clear counter
       EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;   // Clock ratio to SYSCLKOUT
       EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;
       // Setup shadow register load on ZERO
       // Set Compare values
       EPwm4Regs.CMPA.bit.CMPA = EPWM4_CMP;     // Set compare A value : 400
       EPwm4Regs.CMPB.bit.CMPB = EPWM4_CMP;     // Set Compare B value : 400
       // Set actions
       EPwm4Regs.AQCTLA.bit.ZRO = AQ_SET;            // Set PWM1A on Zero
       EPwm4Regs.AQCTLA.bit.CAU = AQ_SET;          // Set PWM1A on event A,
                                                     // up count
       EPwm4Regs.AQCTLB.bit.ZRO = AQ_SET;            // Set PWM1B on Zero
       EPwm4Regs.AQCTLB.bit.CBU = AQ_SET;          // Set PWM1B on event B,
                                                     // up count
       // Set Chopper values
       EPwm4Regs.PCCTL.bit.CHPEN = 1;
       EPwm4Regs.PCCTL.bit.CHPDUTY = 3; // 3 = 50% Duty Cycle
       EPwm4Regs.PCCTL.bit.CHPFREQ = 0; // 0 = No prescale
       // Interrupt where we will change the Compare Values
    //   EPwm4Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;     // Select INT on Zero event
    //   EPwm4Regs.ETSEL.bit.INTEN = 1;                // Enable INT
    //   EPwm4Regs.ETPS.bit.INTPRD = ET_3RD;           // Generate INT on 3rd event

    I get a output of 10MHz and it works with my Delta Sigma hardware.

  • Hi Prakash,

    Thank you for showing another way to generate the same clock using PWM chopper module. However, results are not any different and seem to have same high riplle effect on it as I uploaded earlier.

    I am happy to have found that problem was occuring because of my 8-10inches long wires at GND pin and GPIO pin for convenience in measuring. The inductive parasitics pronounce resonsnce effects at such high frequency of 10MHz. Thus, making Clock signal look worse.

    When measured directly at the GPIO pins of docking station, Clock signal seems to be pretty fine.

    Attached a snapshot of Clock measured directly at GPIO pin of docking station.

    I thank you to take part in this problem determination.