Hello, I need to know if there is a TI core that supports nested interrupts with automatic context save(like a second shadow hardware stack) . I have to find a solution to my design that has to service an external event(high-to-low signal) as soon as it happens despite any ISR in action.
I know how to do it on 24xx core and 28xx core , saving the context and preparing in case of the event, clearing GIE, etc..., but the latency implied ~ 20-30 cycles it may prove to be too much.
I've searched the community but I haven't found relevant answers.
Any suggestions are welcomed.
Thank you.
