Hello, I am using the Experimenter's kit f28m35h52c1 (part #: TMDXDOCKH52C1)
I want to synchronize three epwms to be 120 degrees apart so I can control some thyristors. I followed the example in the document spruh22g to do this and here is what I wrote for my code:
FiAn=217.35*Alpha; // Firing Angle in counts as an integer
PulseW = FiAn+5000; // Pulse width
EPwm1Regs.TBCTL.all = 0; // clear all bits in TBCTL
EPwm1Regs.TBPRD = 65535; // Period = 601 TBCLK counts
EPwm1Regs.CMPA.half.CMPA = FiAn; // Compare A = 200 TBCLK counts
EPwm1Regs.CMPB = PulseW; // Compare B = x TBCLK counts for pulse duration of 30% duty cycle
EPwm1Regs.TBCTR = 0; // clear TB counter
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Phase loading disabled
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV32;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on TBCTR = Zero
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm1Regs.AQCTLA.bit.CBU = AQ_CLEAR;
//EPWM Module 2 config
EPwm2Regs.TBCTL.all = 0; // clear all bits in TBCTL
EPwm2Regs.TBPRD = 65535; // Period = 601 TBCLK counts
EPwm2Regs.CMPA.half.CMPA = FiAn; // Compare A = 200 TBCLK counts
EPwm2Regs.CMPB = PulseW; // Compare B = x TBCLK counts for pulse duration of 30% duty cycle
EPwm2Regs.TBCTR = 0; // clear TB counter
EPwm2Regs.TBPHS.half.TBPHS = 26082; // Phase=120*39123/180
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm2Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Phase loading enabled
EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV32;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm2Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on TBCTR = Zero
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm2Regs.AQCTLA.bit.CBU = AQ_CLEAR;
EPwm3Regs.TBCTL.all = 0; // clear all bits in TBCTL
// EPWM Module 3 config
EPwm3Regs.TBPRD = 65535; // Period = 601 TBCLK counts
EPwm3Regs.CMPA.half.CMPA = FiAn; // Compare A = 200 TBCLK counts
EPwm3Regs.CMPB = PulseW; // Compare B = x TBCLK counts for pulse duration of 30% duty cycle
EPwm3Regs.TBCTR = 0; // clear TB counter
EPwm3Regs.TBPHS.half.TBPHS = 26082; // Phase=120*39123/180
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm3Regs.TBCTL.bit.PHSEN = TB_ENABLE; // Phase loading enabled
EPwm3Regs.TBCTL.bit.PRDLD = TB_SHADOW;
EPwm3Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;// Sync flow through
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // TBCLK = SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV32;
EPwm3Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm3Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO; // load on TBCTR = Zero
EPwm3Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm3Regs.AQCTLA.bit.CBU = AQ_CLEAR;
When I run this code, I find that both epwm2 and epwm3 have been sync to epwm1. I am expecting that epwm2 will be sync to epwm1 and epwm3 will be sync to epwm2. Can anyone please help with this? Here is a picture of what I'm getting
