This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28027: ePWM1&ePWM2 synchronized, Up-down mode, TBPRD:TBPRDHR=0x0018:0100

Part Number: TMS320F28027

Hello,

I want to output ePWM1&2 synchronized in up-down mode.

Could you please advise to solve my problems ?

Q1. EPWM1A(GPIO0) low time is not stable, but sometimes longer by 1 TBCLK.

Q2. EPWM2A(GPIO2) relative phase to EPWM1 is not stable.

Q3. From the result I thought the TBPRDHR should be zero in up-down mode, but is it correct ?

  • This is expected behaviour. Please see the note on p.26 of the HRPWM user's guide for this device:

    "When high-resolution period mode is enabled, an EPWMxSYNC pulse will introduce +/- 1-2 cycle jitter to the PWM (+/- 1 cycle in up-count mode and +/- 2 cycle in up-down count mode). For this reason, TBCTL[SYNCOSEL] should not be set to 1 (CTR = 0 is EPWMxSYNCO source) or 2 (CTR = CMPB is EPWMxSYNCO source). Otherwise the jitter will occur on every PWM cycle with the synchronization pulse."

    Your configuration has SYNCOSEL = 2. All subsequent C2000 devices also have this restriction.

    Regards,

    Richard
  • Richard,

    I appreciate your response.

    Please let me reconfirm that my Q1, that is, the jitters in ePWM1A is also the expected behaviour.
    It was not clear to me whether the p.26 cover the ePWM1A jitter or not.

    It would be clear if your sentence is:
    "When high-resolution period mode is enabled, an EPWMxSYNCI pulse will introduce +/- 1-2 cycle jitter to the PWM . . . "
    In the case the ePWM1A will also be affected.

  • Hello Nambu-san,

    From the waveforms and watch window, it is clear that CMPA = 6, DBRED = 18 and TBPRD = 24. With this configuration, the rising edge (PWM1A) is getting moved from up-count cycle of the time-base counter to the down-count cycle because CMPA+DBRED = 24 = TBPRD. For HRPWM to function correctly, one edge should occur in the up-count cycle and the other in the down-count cycle.

    Also the edges should not violate the duty cycle restrictions described in the user guide. None of the edges should occur within 3 system clock cycles of the zero event and 3 clock cycles of the period event (for HRPRD operation) of the time base counter.

    I hope this helps.

    Hrishi

  • Hrshi and Richard,
    Thank you for your explanation.