LAUNCHXL-F28377S: Data using SigmaDelta Filter Module (SDFM) in Mode 2 (Manchester Encoding) with AMC1306E25 is not Stable

Sandeep,

Your connections looks correct.

Can you please probe for SD1-D2 pin and make sure you don't have noise getting coupled to this pin? I wondering whether your data bits are getting corrupted? It almost looks as if DOUT goes high for a brief period of time. This can happen when (AINP - AINN) >= 320mv

Regards,
Manoj

Manoj,

thank you for your reply. Here you can see an image of the D2 pin:

On further investigation I noticed the following using external Oscillators and the internal PWM as Clock sources with different speeds:

CLK src	CLK speed (MHz)	Power src	Result	Comment
PWM	12,9	3,3V Board	Works	sample code
PWM	20	3,3V Board	Works	sample code
Osc	13	5V ext	Works	sample code
Osc	15	3,3V Board	Works	sample code
Osc	15	3,3V Board	Works	custom code
Osc old	20	3,3V Board	Doesn’t work	Failsave works Clk is not operating synchronously to pwm (jitter visible)
Osc	10	5V board	Works	Clk is not operating synchronously to pwm  (jitter visible)
PWM	10	3,3V Board	Works	sample code new amc
PWM	20	3,3V Board	Works	sample code new amc

Could it be possible that it doesn't work that reliable at high frequencys?

Sometimes it also seems as if the Signal was inverted by the Delfino SDFM as I sometimes get negative Values for positive Voltages. Could this be related? I haven't thought about that being the reason because it is easy to fix (multiply by -1).

 

Kind regards,

Sandesh

Sandesh,

I don't think AMC1306x is unreliable at 20 MHz as it is spec'ed to work at 21 MHz.

Your second observation shouldn't happen. What is the voltage range applied. I believe it is between +/- 250mv for AMC1306E25. Is this correct?

If your differential voltage >= 320mv, then it is possible to obtain negative values for positive voltage. Please check advisory in errata

SDFM: Data Filter Output Does Not Saturate at Maximum Value With Sinc3 and OSR = 256

Regards,
Manoj

Manoj,

thank you for your answer.

Manoj Santha Mohan said:

Sandesh,
 
Your second observation shouldn't happen. What is the voltage range applied. I believe it is between +/- 250mv for AMC1306E25. Is this correct?

If your differential voltage >= 320mv, then it is possible to obtain negative values for positive voltage. Please check advisory in errata

I have the following results:

While applying 0V I get positive and negative values around 0 (which I believe is correct due to noise)

While applying +-5V (clipping voltage) I get inverted readings (+5V -> negative, -5V positive)

While not applying any voltage (FailSave) I get a negative reading. This is probably due to

Manoj Santha Mohan said:

SDFM: Data Filter Output Does Not Saturate at Maximum Value With Sinc3 and OSR = 256

but happens also when I'm using OSR = 64.

Now, while applying +96.8mV (within the specified +-250mV range, adjusted by potentiometer I get a reading of around -79 333 which translates into -96.84mV.

The value is correct, however it is negative. This was just now confirmed with 10MHz but remember it to be the same for most of my testing (that's why I assumed it wasn't a problem).

How can this happen?

kind regards,

Sandesh

Manoj Santha Mohan said:

 
I don't think AMC1306x is unreliable at 20 MHz as it is spec'ed to work at 21 MHz. 

Today I did some further testing as a clock buffer, the CDCLVC1103PWR.

I did some testing with these results:

Clock	Values	Negative?
ext Osc. @ 20MHz	drop	negative Value for positive Voltage (except for 0V)
PWM @ 12 MHz	ok	negative Value for positive Voltage (except for 0V)
PWM @ 16MHz	ok	negative Value for positive Voltage (except for 0V)

I'll try to add a 20MHz PWM test soon.

kind regards,

Sandesh

Sandesh,

I'm getting a feeling whether you are connecting the voltage incorrectly. In short, you are getting positive digital value when negative value is applied and vice versa. Try swapping the wiring of AINP / AINN, your problem should go away.

when (AINP - AINN) = -96.8mv, you are supposed to get negative digital value irrespective of OSR / filter type configuration.
when (AINP - AINN) = +96.8mv, you are supposed to get positive digital value irrespective of OSR / filter type configuration.

Regards,
Manoj

Manoj,

Thank you for your patience.

Manoj Santha Mohan said:

 
when (AINP - AINN) = -96.8mv, you are supposed to get negative digital value irrespective of OSR / filter type configuration.
when (AINP - AINN) = +96.8mv, you are supposed to get positive digital value irrespective of OSR / filter type configuration.

I don't know why but I'm pretty sure this is not the case in my circuit.

On one AMC, I have connected AINP, AINN and GND to GND. The result is a low positive number resembling 0V.

On the other AMC I am testing with I have a potentiometer and a voltage divider so I can adjust the voltage of the AINP pin within the specified range.

AINN is connected to GND. As far as I know, it is impossible to generate a negative Voltage in this circuit.

I have also confirmed the polarity by measuring the voltage with a multimeter.

Are you using 16 bit (or) 32 bit mode? I would recommend you to use 32 bit mode for debug purpose. I'm concerned whether you are right shifting the bits incorrectly.

Also, can you try mode0 instead of mode2 as of now?

-Manoj

I've used both 32bit and 16bit Mode, it does not make a difference.

I cannot try mode0 right now because I only have the Manchester Encoded AMC version currently available.

Sandesh

Sandesh,

Sorry, I was out on vacation. Were you able to get over the problem?

Regards,
Manoj

Manoj,

No, the problem is still not solved. For the moment we are trying to use the PWM as a clock source as this worked fine.

However, using an oscillator would be better since we could place it close to the AMC and avoid routing the PWM through the PCB.

Can please try the following experiment? Both the experiments should use oscillator to clock SD modulators.

Experiment 1
1) Set DOSR = 255 (not DOSR = 256)
2) Apply differential voltage > +320mv and what is the observed output. If possible send me the snapshot of SD_Cx / SD-Dx.

Experiment2
1) Set DOSR = 255 (not DOSR = 256)
2) Apply differential voltage > -320mv and what is the observed output. If possible send me the snapshot of SD_Cx / SD-Dx.

Regards,
Manoj

Hello Manoj,

EDIT:  I messed up some values in this post. The correct results are in the next post. however, the Oscilloscope data is correct and can be seen as reference.

I just completed the experiments. Here are the results using the 20MHz Oscillator (Epson SG-310 series):

Manoj Santha Mohan said:

.

Experiment 1
1) Set DOSR = 255 (not DOSR = 256)
2) Apply differential voltage > +320mv and what is the observed output. If possible send me the snapshot of SD_Cx / SD-Dx. 

This is the SD1_D2 output. The results I get with the Example Code, OSR=255 and 16bit & shift 9 bits is a value of

- 32386 which is constant

(I apply +3.3V on Vinp and Vinn)

Manoj Santha Mohan said:

Can please try the following experiment? Both the experiments should use oscillator to clock SD modulators.

Experiment 1
1) Set DOSR = 255 (not DOSR = 256)
2) Apply differential voltage > +320mv and what is the observed output. If possible send me the snapshot of SD_Cx / SD-Dx. 

this is the SD1_D1 output:

The result I get is - 32386.

this leads to the result that the values are actually negative all the time.

How can this be the case?

As a reference I also include an image of the RAW clk which is fed into the AMC.

Another question: Do you think it is safer to use the not ManchesterEncoded Version (AMC1306Mxx)?

Is it possibly more robust regarding noise etc.?

I have the following results:

Input voltage > (greater) than 320mV:

negative values of around -31880

the values drop even lower every 30 measurements.

Input voltage < (smaller) than -320mV:

positive values of  around 31879

these values also drop every 30 measurements (sometimes they even become negative).

Why is the polarity inverted? I'm very sure I wired everything correctly.

How can this drop happen? This is the thing which actually makes the values unusable. The polarity could easily be switched in Software.

Would you recommend using the not Manchester Encoded version to avoid this kind of problem?

thank you so much for your help!

Sandeep,

When (AINP - AINN) > +320mv

With Sinc3, DOSR = 255, you should get 16581375 in (32 bit mode)

When (AINP - AINN) < -320mv

        With Sinc3, DOSR = 255, you should get -16581375 in (32 bit mode)

It doesn't look like you have the right output. I don't understand why you apply 3.3v to both AINP and AINN. The correct way to do is apply 3.3v to AINP and GND to AINN for (AINP - AINN) > +320mv.

Also, the snapshots you attached weren't much useful because I need both SD-Cx and SD-Dx waveform in one snapshot.

This is what I expect to see

          when (AINP - AINN) > +320mv, SD-Dx should be inverse of SD-Cx

 when (AINP - AINN) < -320mv, SD-Dx should look the same as SD-Cx

Regards,

Manoj

Manoj Santha Mohan said:

Sandeep,

When (AINP - AINN) > +320mv

With Sinc3, DOSR = 255, you should get 16581375 in (32 bit mode)

When (AINP - AINN) < -320mv

        With Sinc3, DOSR = 255, you should get -16581375 in (32 bit mode)

It doesn't look like you have the right output. I don't understand why you apply 3.3v to both AINP and AINN. The correct way to do is apply 3.3v to AINP and GND to AINN for (AINP - AINN) > +320mv.

I used 16bit mode, I can try to verify it on Monday in 32bit mode.

I do not apply 3.3v to AINP and AINN. My explanation was a bit confusing. This should make it clear:

For my measurement of (AINP - AINN) > 320 mV I connected Vdd (which was 5V) to AINP and GND to AINN. This leads to AINP-AINN = 5V > 320mV

For the other measurement (AINP - AINN) < -320mV I connected Vdd (5V) to AINN and GND to AINP. This leads to AINP-AINN = 0V - 5V = -5V < -320mV

Manoj Santha Mohan said:

Also, the snapshots you attached weren't much useful because I need both SD-Cx and SD-Dx waveform in one snapshot.

This is what I expect to see

          when (AINP - AINN) > +320mv, SD-Dx should be inverse of SD-Cx

 when (AINP - AINN) < -320mv, SD-Dx should look the same as SD-Cx

okay. today I was only able to measure on signal at a time, I'll try to do better on Monday.

Sandesh,

I'm concerned that you are tying VDD (5v) to AINP / AINN. It is pretty close to Max limits you can apply on AINP/AINN.

Can you please limit max voltage on AINP/AINN to 1v?

Regards.
Manoj

I apologize for my late response.

Manoj Santha Mohan said:

 
I'm concerned that you are tying VDD (5v) to AINP / AINN. It is pretty close to Max limits you can apply on AINP/AINN.

Can you please limit max voltage on AINP/AINN to 1v?
 

But according to the datasheet it should still be possible.

However, today I made some measurements with a voltage of 1V between AINP and AINN.

here are the results (CLK is red, data is yellow)

AINP > AINN:

and for AINN > AINP:

is this correct?

this is the result for AINP-AINN < -320mV as read by the delfino example project: (with a 20MHz oscillator)

and with AINP-AINN > 320mV:

The voltage applied was 1.0V (positive or negative)

using 12MHz PWM the oscilloscope output is the same (I also confirmed there is a inverted value every 128 clocks as per datasheet).

However, the result is the following:

with AINP-AINN > 320mV (!)

the result is negative and it is not at the maximum range (OSR_64 and 32bit Mode)

Sandesh,

Your oscilloscope shots looks good. But, SDFM filter output isn't correct.

This is what you should see for DOSR = 255 (For DOSR = 255, you should write DOSR = 254. Check the SDDFPARMx register field descriptions). Also, please configure in 32 bit mode. I prefer to read SDDATAx in 32 bit mode instead of array you had attached.

When (AINP - AINN) > +320mv

With Sinc3, DOSR = 255, you should get 16581375 in (32 bit mode)

When (AINP - AINN) < -320mv

        With Sinc3, DOSR = 255, you should get -16581375 in (32 bit mode)

Regards,

Manoj

Manoj,

I just tried to verify this.

Manoj Santha Mohan said:

This is what you should see for DOSR = 255 (For DOSR = 255, you should write DOSR = 254. Check the SDDFPARMx register field descriptions). Also, please configure in 32 bit mode. I prefer to read SDDATAx in 32 bit mode instead of array you had attached.

When (AINP - AINN) > +320mv

With Sinc3, DOSR = 255, you should get 16581375 in (32 bit mode)

When (AINP - AINN) < -320mv

        With Sinc3, DOSR = 255, you should get -16581375 in (32 bit mode)

When (AINP - AINN) > +320mv

With Sinc3, DOSR = 255, I get -16322291 (32bit)

When (AINP - AINN) < -320mv

        With Sinc3, DOSR = 255, I get 16322291 in (32 bit mode)

Sandeep,

Are you using SDFM controlSuite example? (or) is this your own code? I would recommend you try running SDFM_CPU control example code.

If you are already using SDFM example code, then I would look into any hardware issue.

Regards,

Manoj

Perfect, thanks Manoj!

Jens,

I think this thread captures critical inputs which would be very useful for other engineers who face similar issue.

Can you please mark "verify threads" for posts which helped you answer your question.

Regards,
Manoj

I already asked my former colleague to close it, as he started the thread I'm not able to press the verify button...

Thanks
Jens

Jens,

Thanks. This thread has >25 post. Please make sure to verify posts which helped us get to the bottom of this.

Regards,

Manoj