TMS320F28377S: Interrupt latency difference according to ePWM clock prescale

Hi Ted,

For the F2837x & F2807x devices, that the maximum clock rate that the ePWM peripheral can support is 100MHz.  This is described in the datasheet.  As a result, there will at least need to be a /2 divider used (assuming the device is clocked at 200MHz).

I suspect that this may be contributing to what you are seeing.

Hopefully this helps!


Thank you,
Brett 

Hi Brett,

I assumed that for the first time. but clock will be divided through EPWMCLKDIV before the HSPCLKDIV and CLKDV

so the setting below means 100MHz.

EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;   // Clock ratio to SYSCLKOUT

        EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;

Is there other possibility?

Best Regards,

Ted

Hi Ted,

Is the PWM divider the only difference between the two tests?

Can you post waveforms of each scenario and how you are measuring the delay? Please also post your PWM configuration as you indicated you are using a rising edge of the output.

Regards,

Kris

Hi Kris,

I used epwm_up_aq_cpu01.c and disabled PWM2 and PWM3, and only changed PWM divider.

and made the PWM duty 50%, commented the ++and -- in update_compare();

to measure the latency, I added

   GpioDataRegs.GPATOGGLE.bit.GPIO1 = 1;

at the first line of the isr, and here is the waveform.

-div2+div2

-div1+div1

Ted,

Can you post your exact C code so I can try to duplicate this?

On the second image it looks like there may be some jitter on the GPIO toggle. If you do a bunch of "Single" captures does the time ever change? I'm curious if there is another ISR or something occasionally delaying the desired ISR

Regards,

Kris

epwm_up_aq_cpu01.zip

Hi Kris,

I attached the file I used.

Ted