This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.




In the HV Phase Shifted Full Bridge Developer’s kit (TMDSHVPSFBKIT) as well as the Bridgeless Power Factor Correction Converter Kit (TMDSHVBLPFCKIT) I’m changing eg their ..main.c modules to achieve some new functionality.

The assembly code in parts of their …isr.asm content is very time optimized using a lot of NOP’s. I’m afraid to introduce interrupt latency by using C code in the super loop, code that translates to assembly instructions that utilize eg the RPT instruction, since repeat loops are regarded as multicycle instructions and are not interruptible - or other multicycle instructions causing similar interrupt latency.

Do we need to have focus on such issues when modifying the kit’s source code, or will it be taken care of by mechanisms I still not have realized?

The reason for thinking about this potential problem is that I repeatedly observe that the synchronous rectifier control in the Phase Shift FB kit seems to have timing errors when issuing certain (new) C operations in the main.c module. I have not inspected the generated assembly code, but I am almost certain that the C operations that I suspect will end up in multicycle assembly instructions.



  • Hi Consul,

    Usually we want to avoid explicitly introducing RPT instructions in the background loop because, as you correctly identified, this can result in large delays in taking the ISR. I don't think using the C compiler is usually a problem though; this is how the vast majority of applications are built, including ones with time-critical ISRs. I'd recommend you take a look at the generated disassembly to see if you see any long-running multi-cycle operations - if you see these we can work on optimizing them out.
  • Hi Devin,

    Thank you for very fast response to my question! Ok, then we will inspect the disassembly as you suggest, and look for RPT's or other multicycle Assembly instructions. And if we find any occurences, we will look for a work around in Our algorithms.



  • Hi Consul,

    It is important to preserve the NOPs and ISR timing in the HVPSFB implementation with Piccolo 2802x and 2803x devices. The bridgeless PFC code could be converted to C-ISR code without these issues.

    There is an easier way to implement the HVPSFB with type-4 PWM modules that are found on Piccolo F28004x devices. Please refer to the following post for details on how to do this. This allows the ISR to be in C.


    I hope this helps.


  • Hi Hrishi,

    Thanks for helping us With these questions! I will read the post you suggest, and yes in Our Next digital DCDC With synchronous rectification we will look in to the F29004x Family with type-4 PWM. I believe it will make Things much simpler.

    As I described in an earlier post (TMDSHVPSFBKIT: TMDSHVPSFBKIT minimum output voltage.) we are also struggling With the minimum output voltage in this design. Do you have any thoughts about that problem?