In the HV Phase Shifted Full Bridge Developer’s kit (TMDSHVPSFBKIT) as well as the Bridgeless Power Factor Correction Converter Kit (TMDSHVBLPFCKIT) I’m changing eg their ..main.c modules to achieve some new functionality.
The assembly code in parts of their …isr.asm content is very time optimized using a lot of NOP’s. I’m afraid to introduce interrupt latency by using C code in the super loop, code that translates to assembly instructions that utilize eg the RPT instruction, since repeat loops are regarded as multicycle instructions and are not interruptible - or other multicycle instructions causing similar interrupt latency.
Do we need to have focus on such issues when modifying the kit’s source code, or will it be taken care of by mechanisms I still not have realized?
The reason for thinking about this potential problem is that I repeatedly observe that the synchronous rectifier control in the Phase Shift FB kit seems to have timing errors when issuing certain (new) C operations in the main.c module. I have not inspected the generated assembly code, but I am almost certain that the C operations that I suspect will end up in multicycle assembly instructions.