Hello,
I'm actually having a big problem with the ADC conversion on the processor TMS320F28051. The goal is to make continuous conversion on all ADC inputs, with SOC generated by the ADCINT1.
My problem is that some of these measures are correct and some of them not...
After some analyzes, it seams that the inputs creating problems are these defined as ADCINxy (op-amp) in the datasheet (SPRS797B, page 14).
Here is the code I implemented:
void InitADC()
{
EALLOW; /* Allow modification of protected registers */
SysCtrlRegs.PCLKCR0.bit.ADCENCLK = 1; /* Enable ADC clock */
AdcRegs.ADCCTL1.bit.RESET = 1; /* Reset the entire ADC module */
DELAY_US(1); /* Make sure the 2 clock cycles after the reset */
AdcRegs.ADCCTL1.bit.ADCBGPWD = 1; /* Power ADC BG (internal bandgap - internal voltage reference) */
AdcRegs.ADCCTL1.bit.ADCREFPWD = 1; /* Power reference (internal reference buffer) */
AdcRegs.ADCCTL1.bit.ADCPWDN = 1; /* Power ADC (analog circuitry inside the core) */
AdcRegs.ADCCTL1.bit.ADCENABLE = 1; /* Enable ADC */
AdcRegs.ADCCTL1.bit.ADCREFSEL = 0; /* Select internal BG */
EDIS; /* Suspend modification of protected registers */
DELAY_US( ADC_usDELAY ); /* Delay before converting ADC channels */
EALLOW; /* Allow modification of protected registers */
( *Device_cal )( ); /* Calibrate the internal oscillators and ADC with device specific calibration data */
EDIS; /* Suspend modification of protected registers */
DELAY_US( ADC_usDELAY ); /* Delay before converting ADC channels */
AdcOffsetSelfCal();
DELAY_US( ADC_usDELAY ); /* Delay before converting ADC channels */
/* --- Configure ADC --- */
EALLOW; /* Allow modification of protected registers */
AdcRegs.ADCCTL1.bit.INTPULSEPOS = 1; /* ADCINT1 trips after AdcResults latch */
AdcRegs.INTSEL1N2.bit.INT1SEL = 14; /* setup EOC14 to trigger ADCINT1 to fire */
AdcRegs.INTSEL1N2.bit.INT1CONT = 1; /* Enable ADCINT1 Continuous mode */
AdcRegs.INTSEL1N2.bit.INT1E = 1; /* Enabled ADCINT1 */
AdcRegs.ADCSOC0CTL.bit.ACQPS = 0x3F;
AdcRegs.ADCSOC1CTL.bit.ACQPS = 0x3F;
AdcRegs.ADCSOC2CTL.bit.ACQPS = 0x3F;
AdcRegs.ADCSOC3CTL.bit.ACQPS = 0x3F;
AdcRegs.ADCSOC4CTL.bit.ACQPS = 0x3F;
AdcRegs.ADCSOC5CTL.bit.ACQPS = 0x3F;
AdcRegs.ADCSOC6CTL.bit.ACQPS = 0x3F;
AdcRegs.ADCSOC7CTL.bit.ACQPS = 0x3F;
AdcRegs.ADCSOC8CTL.bit.ACQPS = 0x3F;
AdcRegs.ADCSOC9CTL.bit.ACQPS = 0x3F;
AdcRegs.ADCSOC10CTL.bit.ACQPS = 0x3F;
AdcRegs.ADCSOC11CTL.bit.ACQPS = 0x3F;
AdcRegs.ADCSOC12CTL.bit.ACQPS = 0x3F;
AdcRegs.ADCSOC13CTL.bit.ACQPS = 0x3F;
AdcRegs.ADCSOC14CTL.bit.ACQPS = 0x3F;
AdcRegs.ADCSOC15CTL.bit.ACQPS = 0x3F;
AdcRegs.ADCINTSOCSEL1.bit.SOC0 = 1; /* Set ADCINT1 as trigger for the SOC0 */
AdcRegs.ADCINTSOCSEL1.bit.SOC1 = 1; /* Set ADCINT1 as trigger for the SOC1 */
AdcRegs.ADCINTSOCSEL1.bit.SOC2 = 1; /* Set ADCINT1 as trigger for the SOC2 */
AdcRegs.ADCINTSOCSEL1.bit.SOC3 = 1; /* Set ADCINT1 as trigger for the SOC3 */
AdcRegs.ADCINTSOCSEL1.bit.SOC4 = 1; /* Set ADCINT1 as trigger for the SOC4 */
AdcRegs.ADCINTSOCSEL1.bit.SOC5 = 1; /* Set ADCINT1 as trigger for the SOC5 */
AdcRegs.ADCINTSOCSEL1.bit.SOC6 = 1; /* Set ADCINT1 as trigger for the SOC6 */
AdcRegs.ADCINTSOCSEL1.bit.SOC7 = 1; /* Set ADCINT1 as trigger for the SOC7 */
AdcRegs.ADCINTSOCSEL2.bit.SOC8 = 1; /* Set ADCINT1 as trigger for the SOC8 */
AdcRegs.ADCINTSOCSEL2.bit.SOC9 = 1; /* Set ADCINT1 as trigger for the SOC9 */
AdcRegs.ADCINTSOCSEL2.bit.SOC10 = 1; /* Set ADCINT1 as trigger for the SOC10 */
AdcRegs.ADCINTSOCSEL2.bit.SOC11 = 1; /* Set ADCINT1 as trigger for the SOC11 */
AdcRegs.ADCINTSOCSEL2.bit.SOC12 = 1; /* Set ADCINT1 as trigger for the SOC12 */
AdcRegs.ADCINTSOCSEL2.bit.SOC13 = 1; /* Set ADCINT1 as trigger for the SOC13 */
AdcRegs.ADCINTSOCSEL2.bit.SOC14 = 1; /* Set ADCINT1 as trigger for the SOC14 */
AdcRegs.ADCINTSOCSEL2.bit.SOC15 = 1; /* Set ADCINT1 as trigger for the SOC15 */
AdcRegs.ADCSOC0CTL.bit.CHSEL = 0x0; /* set SOC0 channel select to ADCINA0 */
AdcRegs.ADCSOC1CTL.bit.CHSEL = 0x1; /* set SOC2 channel select to ADCINA1 */
AdcRegs.ADCSOC2CTL.bit.CHSEL = 0x2; /* set SOC2 channel select to ADCINA2 */
AdcRegs.ADCSOC3CTL.bit.CHSEL = 0x3; /* set SOC2 channel select to ADCINA3 */
AdcRegs.ADCSOC4CTL.bit.CHSEL = 0x4; /* set SOC2 channel select to ADCINA4 */
AdcRegs.ADCSOC5CTL.bit.CHSEL = 0x5; /* set SOC4 channel select to ADCINA5 */
AdcRegs.ADCSOC6CTL.bit.CHSEL = 0x6; /* set SOC6 channel select to ADCINA6 */
AdcRegs.ADCSOC7CTL.bit.CHSEL = 0x7; /* set SOC6 channel select to ADCINA7 */
AdcRegs.ADCSOC8CTL.bit.CHSEL = 0x8; /* set SOC6 channel select to ADCINB0 */
AdcRegs.ADCSOC9CTL.bit.CHSEL = 0x9; /* set SOC6 channel select to ADCINB1 */
AdcRegs.ADCSOC10CTL.bit.CHSEL = 0xA; /* set SOC6 channel select to ADCINB2 */
AdcRegs.ADCSOC11CTL.bit.CHSEL = 0xB; /* set SOC6 channel select to ADCINB3 */
AdcRegs.ADCSOC12CTL.bit.CHSEL = 0xC; /* set SOC6 channel select to ADCINB4 */
AdcRegs.ADCSOC13CTL.bit.CHSEL = 0xD; /* set SOC6 channel select to ADCINB5 */
AdcRegs.ADCSOC14CTL.bit.CHSEL = 0xE; /* set SOC6 channel select to ADCINB6 */
AdcRegs.ADCSOC15CTL.bit.CHSEL = 0xF; /* set SOC6 channel select to ADCINB7 */
EDIS; /* Suspend modification of protected registers */
}
interrupt void AdcIsr(void)
{
// Acknowledge this __interrupt to receive more __interrupts from group 1
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}
void InitInterrupt()
{
DINT; /* Disable CPU interrupts, this is made as first step in main() */
/* Reinitialize PIE,PIEACK,IER,IFR */
InitPieCtrl(); /* Initialize the PIE control registers */
PieCtrlRegs.PIEACK.all = 0xFFFF; /* Acknowledge all interrupts */
IER &= 0x0000; /* Disable all interrupts */
IFR &= 0x0000; /* Clear all interrupt flags */
/* Map desired ISR's to PieVectTable */
InitPieVectTable( ); /* Initialize the PIE vector table */
EALLOW; /* Allow modification of protected registers */
PieVectTable.ADCINT1 = &AdcIsr; /* Map the ADC 1 interrupt */EDIS; /* Suspend modification of protected registers */
/* PIE-Level Interrupt Enable */
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; /* Enable the PIE */
PieCtrlRegs.PIEIER1.bit.INTx1 = 1; /* Enable ADCINT1 in PIE */
}
int main(void)
{
...
InitInterrupt(); /* Initialize interrupts */
InitADC(); /* Initialize ADC module */
...
IER |= M_INT1; /* Enable CPU Interrupt 1 */
EINT; /* Enable Global interrupt INTM */
ERTM; /* Enable Global Real-Time interrupt DBGM */
AdcRegs.ADCSOCFRC1.bit.SOC14 = 1;
AdcRegs.INTSEL1N2.bit.INT1E = 1;
PieCtrlRegs.PIEIER1.bit.INTx1 = 1;
/* MAIN LOOP */
while(TRUE)
{
...
}
Please, could you tell me where could be the problem? Why only the inputs with the (op-amp) description are creating some problem?
I checked the datasheet and saw that PGA could be a source of changes, but it seams thanothing is configured for the feature...
Thank you very much for your help...
Best
Steve
