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TMDSDOCK28069: EPwm1Regs.TZCTL.bit.DCAEVT1 for cycle-by-cycle

Part Number: TMDSDOCK28069


Hello,
I imported one of the sample project Example_2806xEPwmDCEventTripComp and edited to have ePWM1A to stay high when the comparator1A=ADCINA2 terminal is lower than 1.6V. "cycle-by-cycle".


I got an expected waveform but please let me ask a remaining question.
To set the ePWM1A state under trip, I needed to write {EPwm1Regs.TZCTL.bit.DCAEVT1}.
Why this is not DCAEVT2 but DCAEVT1 ?  I thought the DCAEVT1 is just for one-shot.

Please open the zipped CCS740 project. The project has a result waveform and wiring information for test.


   EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP1OUT;        // DCAH = Comparator 1 output
   EPwm1Regs.DCTRIPSEL.bit.DCALCOMPSEL = DC_TZ2;             // DCAL = TZ2
   EPwm1Regs.TZDCSEL.bit.DCAEVT1 = TZ_DCAH_LOW;              // DCAEVT1 =  DCAH low(will become active as Comparator output goes low) 
   EPwm1Regs.DCACTL.bit.EVT1SRCSEL = DC_EVT1;                // DCAEVT1 = DCAEVT1 (not filtered)
   EPwm1Regs.DCACTL.bit.EVT1FRCSYNCSEL = DC_EVT_ASYNC;       // Take async path


   EPwm1Regs.TZSEL.bit.DCAEVT2 = 1;

   EPwm1Regs.TZCTL.bit.DCAEVT1 = TZ_FORCE_HI;           // EPWM1A will go high
   // My question here: I'm coding cycle-by-cycle but I needed to set DCAEVT1. Why this is not DCAEVT2 ?

/cfs-file/__key/communityserver-discussions-components-files/171/Example_5F00_2806xEPwmDCEventTripComp_5F00_edit_5F00_compbDAC-2-e2e-ccs740.zip

  • Hi Hideaki,

    This is due to TZSEL and TZCTL register functionality differences. The TZSEL register can be configured for one shot (DCAEVT1) vs cycle by cycle (DCAEVT2) as you described, but then TZCTL[TZA/TZB] bits determine what action will be taken on the event caused by TZSEL (in your case, cycle by cycle events). From your attached code, I see you've written to TZCTL[TZA/TZB] so that config will determine the actions.

    Also, different actions with TZCTL have different priorities. The following is a note from the Technical Reference Manual:

    The priority of conflicting actions on the TZCTL register is as follows (highest priority overrides lower
    priority):
    Output EPWMxA: TZA (highest) -> DCAEVT1 -> DCAEVT2 (lowest)
    Output EPWMxB: TZB (highest) -> DCBEVT1 -> DCBEVT2 (lowest)

    Regards,
    Elizabeth
  • Elizabeth,
    Thank you for your reply. Very clear.