Other Parts Discussed in Thread: CONTROLSUITE
Tool/software: Code Composer Studio
Hi,
Could you please help confirm the how the shared memory data exchange being controlled between two cores ?
I'm trying to writing and reading data on both M3 and C28 side, then exchange data through shared memory S0~S7. But I'm wondering do we need to pay special attention when to start writing on one side(eg. C28), then when to start reading on the other side(M3)?
So far my understanding is that we can writing the data on C28 anytime, on the M3 side we can check if there's any available data that's been written to C28, then reading from M3 side.
On C28 side, I plan to have buffer that constantly write or overwrite the data to the shared memory; M3 side also constantly monitoring data on M3 side.
Will that work? Or what would be the typical design if we want use shared memory for the data exchange between two cores?
Thanks,
YZ