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TMS320F280049: ADC synchronization with SDFM

Part Number: TMS320F280049
Other Parts Discussed in Thread: AMC1106M05, AMC1106E05


I want to perform current measurement with SDFM module and AMC1106M05 while measure voltage with internal ADC. For accurate result acquisition I need to get almost synchronous readings from both ADC and SDFM modules, because time shift could introduce unnecessary phase error.

Is there an easy way to synchronize ADC start of conversion event with SDFM data-ready event?


  • Hi Sharihin,

    Someone more knowledgeable about the SDFM module will have to help you determine how to achieve synchronization, but for the on-chip ADC the analog sampling instant is the end of the ADC S+H window.  You'll want to configure the ADC and SDFM timings to line this up with whatever the analog sampling instant is for the external SD ADC. 

    Your results may not become available at exactly the same time, but I'm pretty sure you want the two sampled signals to be sampled at the same time instant? 

  • Hi, Devin

    Yes, I don't really care if SAR ADC data will be available with a little delay: I can change interrupt trigger from SDFM to ADC module and get all readings at once.

    I'm clocking AMC1106E05 device with ECAP module, so, for synchronized data acquisition I need to allocate ePWM module with period equal SDFM sample rate and two SoC events: first one for ADC module with acquistion window delay and second for SDFM sync event.

    Is that correct?
  • Sharihin,

    Are you trying to sample both current and voltage measurement at same time instant using SDFM and ADC respectively? If so, this could be tricky and you have carefully time your events as SDFM is relatively slower converter than ADC. PWM can provide SOC for ADC and SDSYNC event for SDFM. On a SDSYNC event, you have wait for atleast (order of Sinc filter x OSR) + 5) x SD-Cx cycles before reading the correct digital output. You have to time both SDSYNC event and ADCSOC depending upon your requirement.



  • Manoj,

    Do I understand correct: after SDSYNC event and those cycles I'll get value approximately equal as sampling window (sinc * osr * (sysclk/sdclk)) cycles long, and I can place ADC sampling window center right in between this window? After SD data ready interrupt ADC will complete conversion anyway and data will likely be in sync?

  • Dmitry,

    Sampling window for SDFM is (order of Sinc filter x OSR) + 5) x SD-Cx cycles. You should trigger ADCSOC somewhere in the middle of sampling window of SDFM keeping ADC conversion sample window in mind.