Hello Community,
I am trying to calculate the theoretical maximum read and write speed of the EMIF (connected to an ASRAM) of the TMS320F28379D. This should be done only with timing constraints on controller side, ignoring any ASRAM timing constraints.
Making following assumptions:
 Clock running @ 200 MHz
 EMIF clock @ 200 MHz > E = 5 ns
 DMA will be used; 4 cycles / word = 20 ns [datasheet Rev. J, chapter 6.8]
 Busy / wait mode is not used
Using formulas from table 538 [datasheet Rev. J] and looking at figure 521 and 523 respectively, there are a few things I do not understand.
1. Read timing(figure 521)
The read cycle time tc(EMRCYCLE) is number 3 and calculated using the formula:
tc = (RS+RST+RH+2)*E3
With RS,RH at least 1 cycle and RST at least 4 cycles and E = 5 ns this gives:
tc = (1+4+1+2)*5  3 = 37 ns
Looking at figure 521 tc(EMRCYCLE) (number 3) is the time span including the numbers (4  8  6  29) + number 10 + (5  9  7  30), where 4 to 9 and 29, 30 are at least 2 ns and number 10 at least 19 ns. This result in a total of 2 + 19 + 2 = 23 ns.

 Where does the difference of 14 ns (37 ns <> 23 ns) come from?
 When the strobe mode is active, the numbers 4 and 5 are at least 3 ns. How can a wait time span be negative?
2. Write timing (figure 523)
The write cycle time tc(EMWCYCLE) is number 15 and calculated using the following formula:
tc = (WS+WST+WH+2)*E3
With WS, WH and WST at least 1 cycle and E = 5 ns this gives:
tc = (1+1+1+2)*5  3 = 22 ns
Looking at figure 523 tc(EMWCYCLE) (number 15), the time span including the numbers (16  18  20  22) + number 24 + (17  19  21  23), where 16 to 23 are at least 2 ns and number 24 at least 4 ns. This result in a total of 2 + 4 + 2 = 8 ns.

 Where does the difference of 14 ns (22 ns <> 8 ns) come from?
3. Calculate data transfer rate
Calculation of the data transfer rate using the cycle times calculated in 1) and 2) and adding the bus turnaround time of 2 ns:

read 


write 


37 + 2 


22 + 2 

cycle time [ns]: 
39 
39 

24 
24 
data width 
16 
32 

16 
32 






bit rate [MBit/s] 
410,26 
820,51 

666,67 
1333,33 
data rate [MB/s] 
51,28 
102,56 

83,33 
166,67 
In appendix A.1 in "Design and Usage Guidelines for the C2000 EMIF" (SPRAC96A), the asynchronous test configuration uses the fastest possible values for read / write setup, strobe and hold times. These values are the same as assumed in 1) and 2) to calculate the minimum cycle time.
Looking at the diagrams in figure 5 and 6 with a data bus size of 16b, the DMA has a throughput of approximately 80 MB/s (write) and 47 MB/s (read).
Looking at the diagrams in figure 8 and 9 with a data bus size of 16b, the maximum throughput is approximately 78 MB/s (write) and 55 MB/s (read) for the CPU.
While the measured values for the DMA are slightly below the theoretical calculated values, the CPU seems to read a bit faster than the calculated values; but never mind. The question here is:
 Why is data throughput so slow for a 32b data bus size? I would expect the double data rate of the 16b data bus width. Looking at figures 5, 6 and 8, 9 there is a speed increase of about 38% (CPU write), 44% (DMA write), 53%(DMA read) and 80% (CPU read).
With a maximum speed of 4 cycles / word, the DMA has a maximum throughput of 200 MB/s @ 200 MHz and should be fast enough.
 Why is data throughput so slow for a 32b data bus size? I would expect the double data rate of the 16b data bus width. Looking at figures 5, 6 and 8, 9 there is a speed increase of about 38% (CPU write), 44% (DMA write), 53%(DMA read) and 80% (CPU read).