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Watchdog counter update speed in TMS320F2808

Dheeraj Kunnath
Intellectual 350 points

Other Parts Discussed in Thread: TMS320F2808

Hi,

 I would like to know the how fast the watchdog counter will be updated in "TMS320F2808" controller .

The clock speed I am using for system is 100MHz and I would like to implement watchdog in my application, but not sure about the time calculation for watchdog interrupt for system reset?

I can see an 8 bit up counter is used for watchdog and would like to know the maximum time period to fill the counter if I am using a 100Mhz clock for my system.

  • 0
    TI__Guru 61235 points

    Dheeraj,

    The formula for WD timeout in F280x devices is:

         timeout = (1/OSCCLK)*512*256*(FRC rollover)

    where FRC rollover is the rollover count of the WD free running counter.  This is controlled by the WDPS bits in the WDCR register.

    Typically, people use a 20 MHz clock source (e.g., crystal) for the device (and then PLL x5 to operate at 100 MHz).  So, the maximum timeout is calculated with FRC rollover of 64:

        timeout = (1/20 MHz)*512*256*(64) = 0.419 sec.

    Regards,

    David

  • 0 in reply to David M. Alter
    Intellectual 350 points

    Hi David,

     Thanks for the inputs,

    I was referring the datasheet and got confused with the "WDPS settings"

    2-0 WDPS Watchdog pre-scale. These bits configure the watchdog counter clock (WDCLK) rate relative to OSCCLK/512:

    111 WDCLK = OSCCLK/512/64

    So I did calculation as:

    1/((20 MHz/512/64)*256) = 1/((20MHz/8)*256) = 1/(2.5MHz)*256 = 0.4uSec *256 = 102.4uSec.

    Thanks for your support.