TMS320F28069: Action qualification configuration on SDA and SCL induce I2C clock frequency reduction on F28069

Hi Sheldon,

That's good that it has improved.

Q1 Answer: I'm not sure why this clock stretching would be occurring as of now. I'll have to get back to you and may need some additional information to diagnose.

Q2 Answer: Sample window qualification for I2C peripheral pins should be fine. See below from Section 1.5.4, Input Qualification, of the TRM:

For pins that are configured as peripheral inputs, the input can 
also be asynchronous in addition to synchronized to SYSCLKOUT or 
qualified by a sampling window.

Q3 Answer: Not certain right now since Q1 needs to be understood first. Should be OK if the upper monitor can handle clock stretching however.

Some questions for you:

1. With input qualification enabled is it a consistent 70KHz clock? Or does it vary? Curious if the noise on the signals are having some impact.

2. With input qualification disabled is it a consistent 100KHz clock?

3. The device is running at max frequency, 90 MHz, correct? Is an external crystal being used to clock the device?

4. Can you share how the customer is initializing the I2C within software? The important registers in question are shown below:

    I2caRegs.I2CPSC.all = x;		// Prescaler - Should be set so module clock is within 7-12 Mhz
    I2caRegs.I2CCLKL = x;		        // Low portion of SCL, NOTE: must be non zero
    I2caRegs.I2CCLKH = x;		        // High portion of SCL, NOTE: must be non zero

    I2caRegs.I2CFFTX.all = x;	        // TX FIFO mode being used?
    I2caRegs.I2CFFRX.all = x;	        // RX FIFO mode being used?

Best,

Kevin

Hi Sheldon,

I need to retract my answer to Q2 while I acquire more information on our side.

There is the following note in newer device TRMs that has not been carried back to some older device TRMs as of yet:

NOTE: Using input synchronization when the peripheral itself performs the synchronization may

cause unexpected results. The user should ensure that the GPIO pin is configured for

asynchronous in this case.

I will get back to you when I have more information.

Thanks,

Kevin

Hi Kevin,
Thanks for you detailed answer. I will get these answers and back to you!

Hi Kevin,

1. With input qualification enabled is it a consistent 70KHz clock? Or does it vary? Curious if the noise on the signals are having some impact.

Yes, tt is 70KHz constantly. Customers change noise power by adding different load (light/heavy) but no frequency variation is witnessed.

2. With input qualification disabled is it a consistent 100KHz clock?

Yes, consistently 100KHz.

3. The device is running at max frequency, 90 MHz, correct? Is an external crystal being used to clock the device?

Running at 90M with internal OSC.

4. Can you share how the customer is initializing the I2C within software? The important registers in question are shown below:

    I2caRegs.I2CPSC.all = 7;

 

    /*Tmst= ( IPSC_1 )*[ ( ICCL+_d )+_( ICCH_+d ) ] /I2C input clock frequency*/

    I2caRegs.I2CCLKL = 51; /* 100.0kHz */

    I2caRegs.I2CCLKH = 51;

 

    /* Enable FIFO mode and TXFIFO*/

    I2caRegs.I2CFFTX.all = 0x6000;

    /* Enable RXFIFO, clear RXFFINT,*/

    I2caRegs.I2CFFRX.all = 0x2040;

Thanks for your support! My expert.

Hi Kevin,
I'm a software engineer worked for the customer mentioned by Sheldon.
Actually when we found the I2C frequency decrese from 100KHz to 70KHz, we noticed that the IO pin used for I2C clock of Master should not use the qualification function. Then we modify the I2C configuration only in Master
GpioCtrlRegs.GPAQSEL2.bit.GPIO29 = 2;/*6 sample window*/
to GpioCtrlRegs.GPAQSEL2.bit.GPIO29 = 3;/*Asynchronous*/
and it works, the frequency change to 93KHz close to 100KHz.
I don't know why but it should related to the qualification funciton.
Could you explain it?
The other question about if the IO pin used for I2C could be configured for qualification function is mentioned by Sheldon, please help find the answer too.

Thanks!

Hi,
Thanks for the information you provide! Also thanks Joe's advice. I will deliver these information to them through email or phone call tonight.

Hi,

I have been able to recreate what you are seeing on my end. We are working internally to provide an explanation on the clock stretching being seen when using input qualification with a sampling window. As you already know the I2C peripheral performs synchronization itself and asynchronous mode is intended to be used.

I will get back to you when I have more information to share.

Thank you,
Kevin