This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320F28377D: Data out of Sigma-Delta Filter signed and unsigned Problem and high peaks every 200 samples through data processing

Part Number: TMS320F28377D
Other Parts Discussed in Thread: TMS320F28379D, AMC1305M05, CONTROLSUITE

Hi community, I got problems to get the right data out of the Sigma-Delta Filter Module. The bitstream is made by a AMC1305M05 from TI. For filtering I use the integrated SDFM of a TMS320F28379D (ControlCard Version with Docking-Station).
Both sides need a CLK to work correctly and I configured a ePWM-Module on the TMS320F28379D for this. The CLK running with 20 MHz to get detailed data by the most speed.
Now the hardware is adjust to work fine with less as possible noise on the filtered signal.

For the first test I used a project out of  the ControlSuite "sdfm_pwm_sync". The  basic configuration of every SDFM-Data-Filter is a OSR of 64 and Bitshift of 4 Bits let get me exact values, but all Data is in a signed Integer (correct?) Two´s Complement.

At the use of the original Code in CodeComposerStudio there can I also see, that there is a problem with this Data-Type, because CCS interprets everything as unsigned integer. This wrong interpretation also happen, when the data was saved out of the CCS into a csv-file. (Only binaräy Code was right.)
1.How can I easy convert the data to a correct unsigend integer to use the data fast as possible? For example in a inerrupt to oush the data to a register of dac or something else.

The next is that after ~ 200 samples out of the SDFM a peak in the data happens and it can jump to maximum or to the minimum. At first I thought it was a problem at saving the data, because I decided to save more than to 200 samples (in the orignal code 200 data points was the max). Than I changed the code so that the data is not saved on the board and instead a DAC reproduce out of the digital data the orignal waveform. I thought that this will helps agains the peaks, but the peaks are still there. I estimated that peaks still happens after every 200 Sample.
2. What is wrong in my data processing? How can I stop the peaks?

I will give a example scrrenshot from oscilloscope where you can see three Signals produces by DACs. The DACs are feed with data out out of the SDFM of the TMS320F28379D and the bitstream comes from three AMC1305M05 ICs. The measured signal by AMC1305M05 ICs comes from a single signal generator over a voltage divider.



The Code will be here too.

//###########################################################################
//
// FILE:   sdfm_pwm_sync_cpu_cpu01.c
//
// TITLE:  SDFM PWM sync Example for F2837xD.
//
//! \addtogroup cpu01_example_list
//! <h1> SDFM PWM Sync </h1>
//!
//! In this example, SDFM filter data is read by CPU in SDFM ISR routine. The
//! SDFM configuration is shown below:
//!     - SDFM1 is used in this example
//!     - MODE0 Input control mode selected
//!     - Comparator settings
//!         - Sinc3 filter selected
//!         - OSR = 32
//!         - HLT = 0x7FFF (Higher threshold setting)
//!         - LLT  = 0x0000(Lower threshold setting)
//!  -  Data filter settings
//!      - All the 4 filter modules enabled
//!      - Sinc3 filter selected
//!      - OSR = 256
//!      - All the 4 filters are synchronized by using PWM
//!       (Master Filter enable bit)
//!      - Filter output represented in 16 bit format
//!      - In order to convert 25 bit Data filter
//!        into 16 bit format user needs to right shift by 9 bits for
//!        Sinc3 filter with OSR = 256
//!  - Interrupt module settings for SDFM filter
//!      - All the 4 higher threshold comparator interrupts disabled
//!      - All the 4 lower threshold comparator interrupts disabled
//!      - All the 4 modulator failure interrupts disabled
//!      - All the 4 filter will generate interrupt when a new filter data
//!        is available
//!
//
//###########################################################################
// $TI Release: F2837xD Support Library v210 $
// $Release Date: Tue Nov  1 14:46:15 CDT 2016 $
// $Copyright: Copyright (C) 2013-2016 Texas Instruments Incorporated -
//             http://www.ti.com/ ALL RIGHTS RESERVED $
//###########################################################################

//
// Included Files
//
#include "F28x_Project.h"
#include "F2837xD_struct.h"
#include "F2837xD_sdfm_drivers.h"

//
// Defines
//
#define MAX_SAMPLES               200
#define SDFM_PIN_MUX_OPTION1      1
#define SDFM_PIN_MUX_OPTION2      2
#define SDFM_PIN_MUX_OPTION3      3
#define EPWM_TIMER_TBPRD          65535  // ePWM Period register
///////////////////////////////////////////////////////////////////////////////
//Define für ePWM
#define DB_UP              1
//Define für DAC
#define REFERENCE_VDAC      0
#define REFERENCE_VREF      1
#define DACA         1
#define DACB         2
#define DACC         3
#define REFERENCE            REFERENCE_VREF
#define DAC_NUM                DACA
//////////////////////////////////////////////////////////////////////////////

//
// Globals
//
uint16_t gPeripheralNumber, gPWM_number = 11;
uint16_t  Filter1_Result[MAX_SAMPLES];
uint16_t  Filter3_Result[MAX_SAMPLES];
uint16_t  Filter2_Result[MAX_SAMPLES];
uint16_t  Filter4_Result[MAX_SAMPLES];
//////////////////////////////////////////////////////
//Globales für ePWM
Uint16 EPwm7_DB_Direction;
Uint16 EPwm6_DB_Direction;
Uint16 EPwm5_DB_Direction;
Uint16 EPwm4_DB_Direction;
Uint32  EPwm7TZIntCount;
Uint32  EPwm6TZIntCount;
Uint32  EPwm5TZIntCount;
Uint32  EPwm4TZIntCount;
//Glaobales für DAC
volatile struct DAC_REGS* DAC_PTR[4] = {0x0,&DacaRegs,&DacbRegs,&DaccRegs};
/////////////////////////////////////////////////////
#pragma DATA_SECTION(Filter1_Result,"Filter1_RegsFile");
#pragma DATA_SECTION(Filter2_Result,"Filter2_RegsFile");
#pragma DATA_SECTION(Filter3_Result,"Filter3_RegsFile");
#pragma DATA_SECTION(Filter4_Result,"Filter4_RegsFile");

//
// Function Prototypes
//
void Sdfm_configurePins(uint16_t);
void InitEPwm(void);
void done(void);
__interrupt void Sdfm1_ISR(void);
__interrupt void Sdfm2_ISR(void);
///////////////////////////////////////////////////////
//Function Prototypes für ePWM
void InitEPwm7Example();
void InitEPwm6Example();
void InitEPwm5Example();
void InitEPwm4Example();
__interrupt void epwm7_isr(void);
__interrupt void epwm6_isr(void);
__interrupt void epwm5_isr(void);
__interrupt void epwm4_isr(void);
void InitEPwmGpio_TZ(void);
//Function Prototypes für DAC
void configureDAC(Uint16 dac_num);
///////////////////////////////////////////////////////

//
// Main
//
void main(void)
{
   uint16_t  pinMuxoption;
   uint16_t  HLT, LLT;

//
// Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file.
//
    InitSysCtrl();
/////////////////////////////////////////////////
    InitGpio();
    // Einschalten der CLKs der PWM-Module
    //
        CpuSysRegs.PCLKCR2.bit.EPWM7=1;
        CpuSysRegs.PCLKCR2.bit.EPWM6=1;
        CpuSysRegs.PCLKCR2.bit.EPWM5=1;
        CpuSysRegs.PCLKCR2.bit.EPWM4=1;
        InitEPwmGpio_TZ();
/////////////////////////////////////////////////
//
// Clear all __interrupts and initialize PIE vector table:
// Disable CPU __interrupts
//
    DINT;

//
// Initialize PIE control registers to their default state.
// The default state is all PIE __interrupts disabled and flags
// are cleared.
// This function is found in the F2837xD_PieCtrl.c file.
//
    InitPieCtrl();

//
// Disable CPU __interrupts and clear all CPU __interrupt flags:
//
    IER = 0x0000;
    IFR = 0x0000;

//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the __interrupt
// is not used in this example.  This is useful for debug purposes.
// The shell ISR routines are found in F2837xD_SysCtrl.c.
// This function is found in F2837xD_SysCtrl.c.
//
    InitPieVectTable();

//
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
    EALLOW;
    PieVectTable.SD1_INT = &Sdfm1_ISR;
    PieVectTable.SD2_INT = &Sdfm2_ISR;
/////////////////////////////////////////////
    PieVectTable.EPWM7_TZ_INT = &epwm7_isr;
    PieVectTable.EPWM6_TZ_INT = &epwm6_isr;
    PieVectTable.EPWM5_TZ_INT = &epwm5_isr;
    PieVectTable.EPWM4_TZ_INT = &epwm4_isr;
////////////////////////////////////////////
    EDIS;

    EALLOW;
/////////////////////////////////////////////////////////
    //  Alles zwischen den ******* wird synchron ausgeführt durch die Sync Befehle
        EALLOW;
        CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =0;
        EDIS;
    //Intitialisierung/Einstellung der EPWM2 und der EPWM7
        InitEPwm7Example();
        InitEPwm6Example();
        InitEPwm5Example();
        InitEPwm4Example();
        EALLOW;
        CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1;
        EDIS;
/////////////////////////////////////////////////////////

//
// Enable CPU INT5 which is connected to SDFM INT
//
    IER |= M_INT5;
    IER |= M_INT6;//Interrupt für ePWM7
    IER |= M_INT4;
    IER |= M_INT3;
//
// Enable SDFM INTn in the PIE: Group 5 __interrupt 9-10
//
    PieCtrlRegs.PIEIER5.bit.INTx9 = 1;    // SDFM1 interrupt enabled
    //PieCtrlRegs.PIEIER5.bit.INTx10 = 1;   // SDFM2 interrupt enabled
    PieCtrlRegs.PIEIER2.bit.INTx7 = 1;
    PieCtrlRegs.PIEIER2.bit.INTx6 = 1;
    PieCtrlRegs.PIEIER2.bit.INTx5 = 1;
    PieCtrlRegs.PIEIER2.bit.INTx4 = 1;
    EINT;

#ifdef CPU1
    pinMuxoption = SDFM_PIN_MUX_OPTION1;
//
// Configure GPIO pins as SDFM pins
//
    Sdfm_configurePins(pinMuxoption);
#endif

//
// Select SDFM1
//
    gPeripheralNumber = SDFM1;

//
// Input Control Module
//
// Configure Input Control Mode: Modulator Clock rate = Modulator data rate
//
    Sdfm_configureInputCtrl(gPeripheralNumber, FILTER1, MODE_0);
    Sdfm_configureInputCtrl(gPeripheralNumber, FILTER2, MODE_0);
    Sdfm_configureInputCtrl(gPeripheralNumber, FILTER3, MODE_0);
    Sdfm_configureInputCtrl(gPeripheralNumber, FILTER4, MODE_0);

//
// Comparator Module
//
    HLT = 0x7FFF;    //Over value threshold settings
    LLT = 0x0000;    //Under value threshold settings

//
// Configure Comparator module's comparator filter type and comparator's OSR
// value, higher threshold, lower threshold
//
    Sdfm_configureComparator(gPeripheralNumber, FILTER1, SINC3, OSR_32,
                             HLT, LLT);
    Sdfm_configureComparator(gPeripheralNumber, FILTER2, SINC3, OSR_32,
                             HLT, LLT);
    Sdfm_configureComparator(gPeripheralNumber, FILTER3, SINC3, OSR_32,
                             HLT, LLT);
    Sdfm_configureComparator(gPeripheralNumber, FILTER4, SINC3, OSR_32,
                             HLT, LLT);

//
// Enable Master filter bit: Unless this bit is set none of the filter modules
// can be enabled. All the filter modules are synchronized when master filter
// bit is enabled after individual filter modules are enabled. All the filter
// modules are asynchronized when master filter bit is enabled before
// individual filter modules are enabled.
//
    Sdfm_enableMFE(gPeripheralNumber);

//
// Data filter Module
//
// Configure Data filter modules filter type, OSR value and
// enable / disable data filter
//
    Sdfm_configureData_filter(gPeripheralNumber, FILTER1, FILTER_ENABLE, SINC3,
                              OSR_64, DATA_16_BIT, SHIFT_4_BITS);
    Sdfm_configureData_filter(gPeripheralNumber, FILTER2, FILTER_ENABLE, SINC3,
                              OSR_64, DATA_16_BIT, SHIFT_4_BITS);
    Sdfm_configureData_filter(gPeripheralNumber, FILTER3, FILTER_ENABLE, SINC3,
                              OSR_64, DATA_16_BIT, SHIFT_4_BITS);
    Sdfm_configureData_filter(gPeripheralNumber, FILTER4, FILTER_ENABLE, SINC3,
                              OSR_64, DATA_16_BIT, SHIFT_4_BITS);

//
// PWM11.CMPC, PWM11.CMPD, PWM12.CMPC and PWM12.CMPD signals cannot synchronize
// the filters. This option is not being used in this example.
//
    Sdfm_configureExternalreset(gPeripheralNumber,FILTER_1_EXT_RESET_ENABLE,
                                FILTER_2_EXT_RESET_ENABLE,
                                FILTER_3_EXT_RESET_ENABLE,
                                FILTER_4_EXT_RESET_ENABLE);
//
// Init EPWMs
//
    InitEPwm();

//
// Enable interrupts
//
// Following SDFM interrupts can be enabled / disabled using this function.
//  Enable / disable comparator high threshold
//  Enable / disable comparator low threshold
//  Enable / disable modulator clock failure
//  Enable / disable filter acknowledge
//
    Sdfm_configureInterrupt(gPeripheralNumber, FILTER1, IEH_DISABLE,
                            IEL_DISABLE, MFIE_ENABLE, AE_ENABLE);
    Sdfm_configureInterrupt(gPeripheralNumber, FILTER2, IEH_DISABLE,
                            IEL_DISABLE, MFIE_ENABLE, AE_ENABLE);
    Sdfm_configureInterrupt(gPeripheralNumber, FILTER3, IEH_DISABLE,
                            IEL_DISABLE, MFIE_ENABLE, AE_ENABLE);
    Sdfm_configureInterrupt(gPeripheralNumber, FILTER4, IEH_DISABLE,
                            IEL_DISABLE, MFIE_ENABLE, AE_ENABLE);

    while((*EPWM[gPWM_number]).TBCTR < 550);

//
// Enable master interrupt so that any of the filter interrupts can trigger
// by SDFM interrupt to CPU
//
    Sdfm_enableMIE(gPeripheralNumber);
////////////////////////////////////////
//Konfiguration von DAC Aufruf
    configureDAC(DAC_NUM);
////////////////////////////////////////
    while(1);
}

//
// Sdfm1_ISR - SDFM 1 ISR
//
__interrupt void Sdfm1_ISR(void)
{
    //uint32_t sdfmReadFlagRegister = 0;
    //static uint16_t loopCounter1 = 0;

    //
    // Read SDFM flag register (SDIFLG)
    //
    //sdfmReadFlagRegister = Sdfm_readFlagRegister(gPeripheralNumber);
/*
    if(loopCounter1 <= MAX_SAMPLES)
    {
        //
        // Read each SDFM filter output and store it in respective filter
        // result array
        //
        Filter1_Result[loopCounter1] = SDFM1_READ_FILTER1_DATA_16BIT;
        Filter2_Result[loopCounter1] = SDFM1_READ_FILTER2_DATA_16BIT;
        Filter3_Result[loopCounter1] = SDFM1_READ_FILTER3_DATA_16BIT;
        Filter4_Result[loopCounter1++] = SDFM1_READ_FILTER4_DATA_16BIT;

        //
        // Clear SDFM flag register
        //
        Sdfm_clearFlagRegister(gPeripheralNumber,sdfmReadFlagRegister);
        sdfmReadFlagRegister = Sdfm_readFlagRegister(gPeripheralNumber);

        if(sdfmReadFlagRegister != 0x0)
        {
            ESTOP0;
        }
    }
    else
    {
        ESTOP0;
        done();
    }
*/
    //*******************************************
    //Neue Datenverarbeitung mit Ausgabe über DAC

     while(1)
     {
     //Filter1_Result[1] = SDFM2_READ_FILTER1_DATA_16BIT;
     DAC_PTR[DACA]->DACVALS.all = SDFM1_READ_FILTER1_DATA_16BIT;

     DAC_PTR[DACB]->DACVALS.all = SDFM1_READ_FILTER2_DATA_16BIT;

     DAC_PTR[DACC]->DACVALS.all = SDFM1_READ_FILTER3_DATA_16BIT;
     //unsigned int val = (unsigned char)SDFM1_READ_FILTER3_DATA_16BIT[0] << 16 | (unsigned char)SDFM1_READ_FILTER3_DATA_16BIT[1];
     //DAC_PTR[DACC]->DACVALS.all = val;
     }

    //*******************************************
    //
    // Acknowledge this __interrupt to receive more __interrupts from group 5
    //
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
}

//
// Sdfm2_ISR - SDFM 2 ISR
//
__interrupt void Sdfm2_ISR(void)
{
    //uint32_t sdfmReadFlagRegister;
    //static uint16_t loopCounter1 = 0;

    //
    // Read SDFM flag register (SDIFLG)
    //
    //sdfmReadFlagRegister = Sdfm_readFlagRegister(gPeripheralNumber);
/*
    if(loopCounter1 <= MAX_SAMPLES)
    {
        //
        // Read each SDFM filter output and store it in respective filter
        // result array
        //
        Filter1_Result[loopCounter1] = SDFM2_READ_FILTER1_DATA_16BIT;
        Filter2_Result[loopCounter1] = SDFM2_READ_FILTER2_DATA_16BIT;
        Filter3_Result[loopCounter1] = SDFM2_READ_FILTER3_DATA_16BIT;
        Filter4_Result[loopCounter1++] = SDFM2_READ_FILTER4_DATA_16BIT;

        //
        // Clear SDFM flag register
        //
        Sdfm_clearFlagRegister(gPeripheralNumber,sdfmReadFlagRegister);
        sdfmReadFlagRegister = Sdfm_readFlagRegister(gPeripheralNumber);

        if(sdfmReadFlagRegister != 0x0)
        {
             ESTOP0;
        }
    }
    else
    {
        ESTOP0;
        done();
    }
    */
    //*******************************************
    //Neue Datenverarbeitung mit Ausgabe über DAC

    //Filter1_Result[1] = SDFM2_READ_FILTER1_DATA_16BIT;

     DAC_PTR[DACA]->DACVALS.all = SDFM1_READ_FILTER1_DATA_16BIT;


     DAC_PTR[DACB]->DACVALS.all = SDFM1_READ_FILTER2_DATA_16BIT;

     DAC_PTR[DACC]->DACVALS.all = SDFM1_READ_FILTER3_DATA_16BIT;

    //*******************************************
    //
    //
    // Acknowledge this __interrupt to receive more __interrupts from group 5
    //
    PieCtrlRegs.PIEACK.all = PIEACK_GROUP5;
}

//
// Sdfm_configurePins - Configure SDFM GPIOs
//
void Sdfm_configurePins(uint16_t sdfmPinOption)
{
    uint16_t pin;
    switch (sdfmPinOption)
    {
        case SDFM_PIN_MUX_OPTION1:
            for(pin=16;pin<=31;pin++)
            {
                GPIO_SetupPinOptions(pin, GPIO_INPUT, GPIO_ASYNC);
                GPIO_SetupPinMux(pin,GPIO_MUX_CPU1,7);
            }
            break;

        case SDFM_PIN_MUX_OPTION2:
            for(pin=48;pin<=63;pin++)
            {
                GPIO_SetupPinOptions(pin, GPIO_INPUT, GPIO_ASYNC);
                GPIO_SetupPinMux(pin,GPIO_MUX_CPU1,7);
            }
            break;

        case SDFM_PIN_MUX_OPTION3:
            for(pin=122;pin<=137;pin++)
            {
                GPIO_SetupPinOptions(pin, GPIO_INPUT, GPIO_ASYNC);
                GPIO_SetupPinMux(pin,GPIO_MUX_CPU1,7);
            }
            break;
    }
}

//
// InitEPwm - Initialize specified EPWM settings
//
void InitEPwm(void)
{
    uint16_t CMPC,CMPD;

    CMPC = 2;
    CMPD = 2;

#ifdef CPU1
    GPIO_SetupPinOptions(4, GPIO_OUTPUT, GPIO_ASYNC);
    GPIO_SetupPinMux(4,GPIO_MUX_CPU1,1);
#endif

    EALLOW;

    //
    // Allows all users to globally synchronize all enabled ePWM modules to
    // the time-base clock (TBCLK)
    //
    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;

    //
    // Setup TBCLK
    //
    (*EPWM[gPWM_number]).TBPHS.bit.TBPHS = 0x0000;    // Phase is 0
    (*EPWM[gPWM_number]).TBCTR = 0x0000;              // Clear counter
    (*EPWM[gPWM_number]).TBPRD = EPWM_TIMER_TBPRD;    // Set timer period
                                                      // 801 TBCLKs.

    (*EPWM[gPWM_number]).CMPC = CMPC;                 // Set Compare C value
    (*EPWM[gPWM_number]).CMPD = CMPD;                 // Set Compare D value

    (*EPWM[gPWM_number]).CMPA.bit.CMPA = CMPC;        // Set Compare C value
    (*EPWM[gPWM_number]).CMPB.bit.CMPB = CMPD;        // Set Compare D value

    //
    // Setup counter mode
    //
    (*EPWM[gPWM_number]).TBCTL.bit.CTRMODE = TB_COUNT_UP; // Count up
    (*EPWM[gPWM_number]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
    (*EPWM[gPWM_number]).TBCTL.bit.CLKDIV = TB_DIV1;

    //
    // Set actions
    //
    (*EPWM[gPWM_number]).AQCTLA.bit.CAU = 3;      // Set PWM1A on event A, up
                                                  // count

    //
    // Set actions
    //
    (*EPWM[gPWM_number]).AQCTLB.bit.CBU = 3;      // Set PWM1A on event A, up
                                                  // count

    EDIS;
}

//
// done - Function to halt debugger and stop application
//
void done(void)
{

    asm(" ESTOP0");
    for (;;);
}
//////////////////////////////////////////////////////////////////////////////////////////
void InitEPwmGpio_TZ(void)
{
    EALLOW;
    GpioCtrlRegs.GPAPUD.bit.GPIO12 = 1;    // Disable pull-up on GPIO10 (EPWM7A)
    GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1;   // Configure GPIO10 as EPWM7A
    GpioCtrlRegs.GPAPUD.bit.GPIO13 = 1;    // Disable pull-up on GPIO11 (EPWM7B)
    GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1;   // Configure GPIO11 as EPWM7B

    GpioCtrlRegs.GPAPUD.bit.GPIO10 = 1;    //EPWM6A
    GpioCtrlRegs.GPAMUX1.bit.GPIO10 = 1;   //
    GpioCtrlRegs.GPAPUD.bit.GPIO11 = 1;    //EPWM6B
    GpioCtrlRegs.GPAMUX1.bit.GPIO11 = 1;   //

    GpioCtrlRegs.GPAPUD.bit.GPIO8 = 1;    //EPWM5A
    GpioCtrlRegs.GPAMUX1.bit.GPIO8 = 1;   //
    GpioCtrlRegs.GPAPUD.bit.GPIO9 = 1;    //EPWM5B
    GpioCtrlRegs.GPAMUX1.bit.GPIO9 = 1;   //

    GpioCtrlRegs.GPAPUD.bit.GPIO6 = 1;    //EPWM4A
    GpioCtrlRegs.GPAMUX1.bit.GPIO6 = 1;   //
    GpioCtrlRegs.GPAPUD.bit.GPIO7 = 1;    //EPWM4B
    GpioCtrlRegs.GPAMUX1.bit.GPIO7 = 1;   //
    EDIS;
}
//
// End of file
//
//EPM7 nur für Test-Zwecke
void InitEPwm7Example()
{
    EALLOW;

    EPwm7Regs.TBPRD = 4;
    EPwm7Regs.TBPHS.bit.TBPHS = 0x0000;
    EPwm7Regs.TBCTR = 0x0000;

    EPwm7Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
    EPwm7Regs.TBCTL.bit.PHSEN = TB_DISABLE;
    EPwm7Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
    EPwm7Regs.TBCTL.bit.CLKDIV = TB_DIV1;

    EPwm7Regs.CMPA.bit.CMPA = 2;
    EPwm7Regs.AQCTLA.bit.ZRO =AQ_SET;
    EPwm7Regs.AQCTLA.bit.CAU = AQ_CLEAR;

    EPwm7Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm7Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    EPwm7Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm7Regs.DBRED.bit.DBRED = 0;
    EPwm7Regs.DBFED.bit.DBFED = 0;
    EPwm7_DB_Direction = DB_UP;

    EPwm7Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;
    EPwm7Regs.ETSEL.bit.INTEN = 1;
    EPwm7Regs.ETPS.bit.INTPRD = ET_3RD;
    EDIS;
}
__interrupt void epwm7_isr(void)
{

    EPwm7Regs.ETCLR.bit.INT = 1;

}
//
//EPM7 nur für Test-Zwecke
void InitEPwm6Example()
{
    EALLOW;

    EPwm6Regs.TBPRD = 4;
    EPwm6Regs.TBPHS.bit.TBPHS = 0x0000;
    EPwm6Regs.TBCTR = 0x0000;

    EPwm6Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
    EPwm6Regs.TBCTL.bit.PHSEN = TB_DISABLE;
    EPwm6Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
    EPwm6Regs.TBCTL.bit.CLKDIV = TB_DIV1;

    EPwm6Regs.CMPA.bit.CMPA = 2;
    EPwm6Regs.AQCTLA.bit.ZRO =AQ_SET;
    EPwm6Regs.AQCTLA.bit.CAU = AQ_CLEAR;

    EPwm6Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm6Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    EPwm6Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm6Regs.DBRED.bit.DBRED = 0;
    EPwm6Regs.DBFED.bit.DBFED = 0;
    EPwm6_DB_Direction = DB_UP;

    EPwm6Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;
    EPwm6Regs.ETSEL.bit.INTEN = 1;
    EPwm6Regs.ETPS.bit.INTPRD = ET_3RD;
    EDIS;
}
__interrupt void epwm6_isr(void)
{

    EPwm6Regs.ETCLR.bit.INT = 1;

}
//
//EPM7 nur für Test-Zwecke
void InitEPwm5Example()
{
    EALLOW;

    EPwm5Regs.TBPRD = 4;
    EPwm5Regs.TBPHS.bit.TBPHS = 0x0000;
    EPwm5Regs.TBCTR = 0x0000;

    EPwm5Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
    EPwm5Regs.TBCTL.bit.PHSEN = TB_DISABLE;
    EPwm5Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
    EPwm5Regs.TBCTL.bit.CLKDIV = TB_DIV1;

    EPwm5Regs.CMPA.bit.CMPA = 2;
    EPwm5Regs.AQCTLA.bit.ZRO =AQ_SET;
    EPwm5Regs.AQCTLA.bit.CAU = AQ_CLEAR;

    EPwm5Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm5Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    EPwm5Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm5Regs.DBRED.bit.DBRED = 0;
    EPwm5Regs.DBFED.bit.DBFED = 0;
    EPwm5_DB_Direction = DB_UP;

    EPwm5Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;
    EPwm5Regs.ETSEL.bit.INTEN = 1;
    EPwm5Regs.ETPS.bit.INTPRD = ET_3RD;
    EDIS;
}
__interrupt void epwm5_isr(void)
{

    EPwm5Regs.ETCLR.bit.INT = 1;

}
//
//EPM7 nur für Test-Zwecke
void InitEPwm4Example()
{
    EALLOW;

    EPwm4Regs.TBPRD = 4;
    EPwm4Regs.TBPHS.bit.TBPHS = 0x0000;
    EPwm4Regs.TBCTR = 0x0000;

    EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
    EPwm4Regs.TBCTL.bit.PHSEN = TB_DISABLE;
    EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
    EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;

    EPwm4Regs.CMPA.bit.CMPA = 2;
    EPwm4Regs.AQCTLA.bit.ZRO =AQ_SET;
    EPwm4Regs.AQCTLA.bit.CAU = AQ_CLEAR;

    EPwm4Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
    EPwm4Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
    EPwm4Regs.DBCTL.bit.IN_MODE = DBA_ALL;
    EPwm4Regs.DBRED.bit.DBRED = 0;
    EPwm4Regs.DBFED.bit.DBFED = 0;
    EPwm4_DB_Direction = DB_UP;

    EPwm4Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;
    EPwm4Regs.ETSEL.bit.INTEN = 1;
    EPwm4Regs.ETPS.bit.INTPRD = ET_3RD;
    EDIS;
}
__interrupt void epwm4_isr(void)
{

    EPwm4Regs.ETCLR.bit.INT = 1;

}
// configureDAC - Configure specified DAC output
//Abänderung -->Konfiguration von zwei DACs
void configureDAC(Uint16 dac_num)
{
    EALLOW;
    DacaRegs.DACCTL.bit.DACREFSEL = REFERENCE;
    DacaRegs.DACOUTEN.bit.DACOUTEN = 1;
    DacaRegs.DACVALS.all = 0;
    //DELAY_US(10); // Delay for buffered DAC to power up
    DacbRegs.DACCTL.bit.DACREFSEL = REFERENCE;
    DacbRegs.DACOUTEN.bit.DACOUTEN = 1;
    DacbRegs.DACVALS.all = 0;
    //DAC_C
    DaccRegs.DACCTL.bit.DACREFSEL = REFERENCE;
    DaccRegs.DACOUTEN.bit.DACOUTEN = 1;
    DaccRegs.DACVALS.all = 0;
    DELAY_US(10); // Delay for buffered DAC to power up
    EDIS;
}



Thanks in Advanced

  • Basti,

    From your code settings, SDFM data filter's data rate = 3.2us and PWM synchronizes SDFM data filters every 655.35 us. In 655.35 us window, SDFM data filter generates around 204-205 (655.35 us / 3.2 us) new filter results. Everytime filters are synchornized, it is expected to get 2 incorrect filter samples immediately after PWM synchronization for Sinc3 filter. This is the reason why you see low peaks every ~200 samples. You need to ignore these 2 incorrect samples immediately after PWM synchronization and then start recording the SDFM filter results.

    SYSCLK

    200 MHz

    SD-Cx

    20 MHz

    PWMCLK

    100 MHz

    DOSR

    64

    TBPRD

    65535

    SDFM data rate

    3.2 us

    PWM SYNC rate

    655.35 us

     I didn't understand your first question on signed / unsigned. But, data filter output is a signed value.

    Regards,

    Manoj

  • Glad to know this issue is resolved. I'm closing this thread.

    -Manoj
  • Thanks Manoj, for your fast answer. This really helps me to understand the Sigma-Delta-Filters better. But to hear that there will be always a peak in my data, is not so good. To ignore the peak is not the problem, but the missed data will be a problem for the future application with this controller.

    To my first question which is really basic. Programming in c is not my area of expertise. And by now I tried differnt ways to convert the data to a unsigned integer and only use 12-bit of it, but nothing really works. I want to do this because the interal DAC of my controller only with unsigned values (12-Bit). The Outputted Signal I want to compare the output signal of closed-loop compensation transformer (automotive).
    If you can´t give me a example for this, than I will find a way, but it will takes really longer...

    Basti
  • Basti,

    In your example, you need to add 16384 to 16 bit filter result output to convert signed filter output value to unsigned value.

    Refards,
    Manoj
  • Hi Manoj,

    thanks for your reply! This was my first idea to convert to unsigned, but it didn't work.
    So I startet to look afer a command for translation.
    Now with this answer I tried it again and now it is clear why it doesn´t work, because I have to use the values as a a hex-value and not dec.

    These really helps me.
    Thanks

    regards basti