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TMS320F280049: ADC clamping external voltage level to below 2.2V when supplied with a resistor divider

Part Number: TMS320F280049

Hi expert,

We are sampling HV DC through voltage divider into ADCs. We met some problem that the divided voltage signal is clamped on some channels (can not go up than 2.2V when increase HV DC, reference is 3.3V) where these pins are connected to multiple ADC inputs such as pin 36 in 100 pin package. But this problem will not happen on pins connected with only one ADC input such as pin 38 in 100 pin package.

We already tested these ADC channels with signal source, everything is fine with a strong source. So we would like to know the reason behind this phenomenon. Did these pins get different input impedence?

We'd like to do some test by directly route signal (divided HV DC) into ADC through PAG_OF pin with ADC input disabled. Is that possible?

Thanks

Sheldon

  • Hi Sheldon,

    Has the PGA been used/enabled when this clamping condition occurred? Reason I am asking is that pin 36 on the 100P device is the PGA OF pin of PGA2 and there are some internal resistances that are involved if PGA is used. Is it possible to get the input schematics and ADC/(PGA if used) setup routines?

    As for directly driving the PGA_OF while disabling ADC input, this is not possible since all PGA_OF channels are directly connected to ADC inputs (no mux option). Please refer to table 12-1 of the Analog Subsys section on the TRM.

    Best regards,
    Joseph
  • Hi Joseph,

    PGA is not enabled and both PGA_IN and PGA_GND connected to ground.

    They divided a HV DC using 480k and 2.49k divider, a 470 ohm serial resistor in the ADC path.

    They give me two additional questions related to this issue.

    1. When PAG_IN and PGA_GND is connected to ground and this PGA is disabled. Will the impedence from PGA_IN to PGA_OF be the same with the impedence from PGA_OF to PGA_IN?

    2. IF PGA is disabled. Will influence come in from PGA input?

    BTW, I find this on TRM. I really need your help for a better understanding on this.

    1. Does the two "To ADC and CMPSS" the same physical connect?

    2. Does the switch in red circle a tri state switch? If this switch is connected to the ground, will the PGA_OF pin been draw to ground?

    Thanks

    Sheldon

  • Hi Sheldon,

    Please see my response to below questions:

    1. When PAG_IN and PGA_GND is connected to ground and this PGA is disabled. Will the impedence from PGA_IN to PGA_OF be the same with the impedence from PGA_OF to PGA_IN?

    Ans:  Not sure I follow the question because if PGA_IN is connected to GND, then impedance of PGA_IN is essentially at GND.  Impedance of PGA_OF though will be some finite value.

    2. IF PGA is disabled. Will influence come in from PGA input?

    Ans:  This really depends on how or if the PGA is set up earlier then disabled.  The PGAEN switch by default is connected to VSSA (GND) if PGA is disabled, cutting off the op amp output.  If however, PGACTL.FILTRESSEL has been programmed to a value earlier, then PGA is disabled and peripheral clock to PGA is disabled, the FILTRESSEL value holds and there will be a resistance from PGA_OF to VSSA (GND).  Please check if customer is enabling PGA clock and writing to any of the PGA registers, even if PGA is disabled as this will cause some of the resistance path to be closed.

    And to answer your TRM-related questions:

    1. Does the two "To ADC and CMPSS" the same physical connect?

    Ans: No they are not.  These are two different internal signals going to different ADC and CMPSS channels.  This is illustrated in Table 12-1 on the TRM (Analog Subsys section)

    2. Does the switch in red circle a tri state switch? If this switch is connected to the ground, will the PGA_OF pin been draw to ground?

    Ans: This is not a tristate switch.  If PGA is disabled, this switch connects to GND, otherwise it connects to the output of the PGA.

    Hopefully these information helps isolate the clamping issue seen by customer.

    Best regards,

    Joseph

  • Hi Joseph,

    I understand your answers. Thanks!

    For question "Does the two "To ADC and CMPSS" the same physical connect?" could you check if my understanding is right or not:

    When not using a PGA, signal come into PGA1_OF which can be sampled by ADCA2 and ADCB6.

    When using PGA1_IN as input, but not using output filter, the amplified signal can be sampled by ADCA11 and ADCB7.

    When using PGA1_IN as input and using output filter, the amplified signal can be sampled by ADCA11 and ADCB7 and the filtered signal after PGA output can be sampled by ADCA2 and ADCB6.

    All the circumstances above can bus CMPSS1.

    Internal signals are like this:

    Thanks 

    Sheldon

  • Hi Sheldon,

    Yes, your understanding is correct.