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TMS320F28379D: Interrupt Servicing

John Churchill
Intellectual 260 points

Part Number: TMS320F28379D
Other Parts Discussed in Thread: C2000WARE

After troubleshooting my main application which is missing ADC interrupts I found that interrupts in lower rows are not interrupted by interrupts on higher rows. To confirm I took your CPU_TIMERS example and modified it to toggle a GPIO for each of the timers. I changed the repetition rate to be faster and to be odd values to assure that they would interrupt each other. I them put a 3000uS delay in each interrupt to simulate a lot of processing. Looking on a scope I can see that no interrupt routine is ever interrupted by another. Regardless of the row, they only interrupt when there are no other interrupts pending. Can someone tell me what I am doing wrong? If you need me to zip up the modified CPU_TIMERS demo I can because it is very simple!

Thanks!

  • 0
    TI__Mastermind 27200 points
    John,

    That is correct - you're not doing anything wrong. The C28x does not operate a pre-emptive hardware interrupt prioritization scheme. The only time prioritization takes place is if two interrupts occur in the same clock cycle: then the lower row number and lower PIE number takes priority. Once an interrupt is taken by the core the global interrupt mask is set.

    You can use software to implement interrupt prioritization and there is an example of this in the peripheral header files in C2000Ware. There is more information in Chapter 3 of the System Control & Interrupts Guide (spru430).
    www.ti.com/.../spru430f.pdf

    I hope this helps.

    Regards,

    Richard
  • 0 in reply to Richard Poley
    Intellectual 260 points

    Thanks Richard,

    Too many years of Motorola processors. I get it.

    John