Hello,
colleagues of mine identified that the CAN communication stops in a test setup at a random time with a TMS320F28067 processor. We connected to the non-communicating CPU via JTAG (without loading a new firmware image and also without resetting the CPU in order to preserve the error situation).
We use Mailbox 0 in Tx direction. We see that Mailbox 0 holds a message and the corresponding transmit request bit inside register CANTRS is being set but never cleared by the peripheral. So it looks like the CAN controller stops transmitting the message located inside Mailbox 0. We also measured via oscilloscope that the CAN_TX pin of the CPU has always a high level, so no messages are being transmitted.
Here is a screen-shot of the relevant registers:
The registers that we checked are:
CANME = 63 -> Mailbox 0…5 are enabled.
CANMD = 62 -> Mailbox 0 is selected as a Tx Mailbox.
CANTRS bit 0 -> TRS0=1, which means a transmit request has been set for Mailbox 0. We expect this bit to get 0 after the message is being shifted out but this never happens.
CANES = 16 -> No power down or bus-off state. So no error indication that would prevent a transmission of a CAN telegram.
CANTEC = 0 -> No transmission error.
CANTIOC = 9 -> CANTX pin is used for transmission.
CANTSC is incrementing, which means CAN controller is clocked.
Can you please help us to check why the CPU stops suddenly shifting our messages on the CAN bus? Is there any further register we can look at?
Best regards,
Andreas