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TMS320F28067: Minimum current consumption

Part Number: TMS320F28067

Hello,

Does TI have any minimum current consumption data?

I am seeing big variations of the supply current during the initial flash programming (entered through bootloader SCI communication). Some of our applications inject current into the ESD reverse diodes of the MCU pins, limited to a few milliamps. In this situation, some boards cannot be initially programmed with firmware, as the supply voltage rises over the reset supervisor threshold (over ~3.6V).

Does TI has any minimum current conpumption value, during flash programming (when MCU control is in the hands of bootloader / OTP flash programming library)?

  • Alecsandru,

    We do not have a minimum current specified for our devices.

    In general we would recommend not injecting current into the ESD diodes routinely.  This can disturb the device VDDIO supply and possibly alter the function of the device unexpectedly.   So my first recommendation would be to eliminate the current injection if possible.  If it is not possible to eliminate the the injection, then limit it to as low a current as possible.

    It looks like you are seeking the current load to target as you reduce the injection current.  Since we don't specify a minimum load (and it could be relatively small depending on the device activity), then I suggest placing a DC resistive load on VDDIO in the PCB or test harness that matches or exceeds your total injected current to ensure this supply does not rise above the regulated 3.3v level.  This should prevent the supervisor trip in your situation.

    Best regards,

    Jason

  • I'll explain more in detail:

    In some applications, we implement down-conversion from 5V to 3.3V using the on-chip ESD / clamp diode, which exists on-chip between processor (MCU) pin(s) and processor 3.3V supply. We add a series resistor between the external 5V signal, and the MCU pin. When signal is at 5V, the diode inside MCU will conduct, and will limit the MCU pin voltage to ~ 3.3V + 0.5V ~= 3.8V. We make sure that the resistor is large enough to limit the current per pin below I_IK, and below the total clamp current I_IKTOTAL (from device datasheet, table 5.1).

    But in this situation, the clamp current passing through the ESD diode arrives into the 3.3V supply. We are using in these applications an LDO, i.e. the supply is not able to sink current.

    If the current injected through the ESD diodes is larger than the total current consumption on 3.3V rail, then the 3.3V voltgae will rise. This rise is intercepted by the on-chip OVR (overvoltage reset) circuitry, which asserts reset.

    We encounter sometimes this situation during the initial firmware programming, on a fresh new device, when we use bootloader in SCI (serial / RS232) mode to upload the firmware: the flash write / erase procedure is sometimes interrupted by a reset. Adn this situation loops enflessly.

    To avoid this situation, we applied the workaround to add a ballast resistor between 3.3V anf GND, to have always some current consumption. But I want to minimize the extra power sissipation introduced by this workaround, thus I need a minimum current consumption of the processor.

    I know that another workaround is to add a shunt regulator across 3.3V anf GND, but this is not feasible on existing / launched boards.

  • Alecsandru,

    Thanks for the additional detail, I can understand the situation.

    I would generally recommend avoiding this current injection on a continuous basis.  Table 5-1 is the Absolute Maximum rating.  The more relevant table for operational modes would be 5-3 Recommended Operating Conditions; in this table we recommend to keep Vih below VDDIO+0.3V.  Keeping below this level will ensure the VDDIO power supply is not disturbed from current injections.  A level shifting buffer on this input or a resistor voltage divider could be better solutions than using the series resistor and internal ESD diode.

    But, if you cannot change existing boards then a ballast resistor may be the only option.  The 3.3v VDDIO supply intrinsically has very low quiescent current (microamps).  The VDDIO supply current really just depends on the IO activity itself for inputs and outputs.  Since this will depend on your application we can't specify a minimum.  You could configure an unused output buffer to drive high into a resistive load whenever the 5v input is present; in this way you could minimize the ballast current penalty to only the duration of the over-voltage event.  This may not work in startup cases before code is loaded though.  You could also have a ballast resistor activated directly on the board with a series FET that is enabled by the 5v signal, but that is back to board modifications.

    I'm sorry I don't have better ideas for you.

    Best regards,

    Jason