TMDSCNCD28027: How to reset the ramp generator when the phase is terminated by a sync event and doesn't reach TBPRD.

Tommy,

This is a variable frequency LLC with peak charge mode control (PQMC).  PQMC works similar to peak current mode control in a buck, except rather than the comparator determining the duration of one phase at a fixed frequency, two comparators each control the duration of one of two phases (+ and -).  So when the comparators are in control, the period of each phase and hence the switching frequency are variable.

EPWM1 drives the primary side switch with complementary outputs A & B.  Its TBPRD is set to the maximum period, so if the comparators don't trip, the EPWM1 outputs toggle at the max period.  If the comparators trip, they create a sync event that resets the EPWM1 counter and force the outputs to toggle.  But I also need to set a minimum period.  I am using the blanking window to prevent the comparators from resetting EPWM1 before the minimum period has expired.  I use EPWM4 to generate a PWMSYNC signal that starts the ramp generators in the comparators immediately after the minimum period has expired and the blanking window terminates.  That prevents premature resetting of the ramp generator during the blanking window.

My issue occurs when the comparators do not trip during a given phase, so EPWM1 times out at TBPRD.  This resets EPWM1 but not the ramp generators in the comparators - they keep counting down into the next cycle.  This can produce premature triggering of the comparator while the blanking window is active early in the next cycle, because the comparator reference will be too low.  Two bad things can happen when the comparator trips too soon: 1) the period can be terminated prematurely if the trip occurs after the blanking window, creating a too short period; 2) the ramp generator can be reset prematurely if the trip occurs before the blanking window terminates, creating a too long period.

Anyway, my solution seems to be working well now and the ISR is fast enough after some improvements.  This is the code that I execute every cycle in the ISR:

EALLOW;
if(GpioDataRegs.GPADAT.bit.GPIO0)
{ // EPWM1 output A is high, enable COMP1
EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP1OUT; // select COMP1 as input to event filter
Comp1Regs.DACCTL.bit.DACSOURCE = 1; // 1 - Internal ramp for slope compensation
Comp2Regs.DACCTL.bit.DACSOURCE = 0; // 0 - DACVAL;
}
else
{ // EPWM1 output B is high, enable COMP2
EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = DC_COMP2OUT; // select COMP2 as input to event filter
Comp2Regs.DACCTL.bit.DACSOURCE = 1; // 1 - Internal ramp for slope compensation
Comp1Regs.DACCTL.bit.DACSOURCE = 0; // 0 - DACVAL;
}
EDIS;

For reference, this is how the EPWM1, EPWM4, and Comparators are configured:

EALLOW;

// Configure ePWM1AB (used to switch primary half-bridge FETs)

// Time-Base Submodule Registers
EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW; // set load on CTR=0
EPwm1Regs.TBPRD = MAX_PERIOD-1; // PWM frequency = 1 / period
EPwm1Regs.TBCTR = 0;
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm1Regs.TBCTL.bit.PHSEN = 1; // 1 = enable loading counter register from phase register
EPwm1Regs.TBCTL.bit.SYNCOSEL = 1; // 1 = sync output when counter = 0
EPwm1Regs.TBPHS.half.TBPHS = 0; // phase register value
// Counter-Compare Submodule Registers
EPwm1Regs.CMPA.half.CMPA = 0; // set duty 0% initially
EPwm1Regs.CMPB = 0; // set duty 0% initially
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;
// Digital Compare Submodule Registers
EPwm1Regs.DCTRIPSEL.bit.DCAHCOMPSEL = 8; // 8 = DCAH = Comparator 1 output initially (ISR switches this between Comp1 and Comp2 each phase)
EPwm1Regs.TZDCSEL.bit.DCAEVT1 = 2; // 2 = DCAEVT1 set on DCAH high(will become active as Comparator output goes high)
EPwm1Regs.DCACTL.bit.EVT1SRCSEL = 1; // 1 = Use filtered DCEVTFILT Signal (filtered by event window, see below)
EPwm1Regs.DCACTL.bit.EVT1SYNCE = 1; // 1 = SYNC Generation Enabled
EPwm1Regs.TZCTL.bit.DCAEVT1 = 3; // 3 = Do nothing on EPWM1A output on event
EPwm1Regs.DCFCTL.bit.SRCSEL = 0; // 0 = Filter source = DCAEVT1
EPwm1Regs.DCFCTL.bit.PULSESEL = 1; // 0 = Filter start on TBCTR = 0
EPwm1Regs.DCFCTL.bit.BLANKE = 1; // 1= Enable Blanking window
EPwm1Regs.DCFCTL.bit.BLANKINV = 0; // 0 = Blanking window not inverted
EPwm1Regs.DCFOFFSET = 0; // Set filter offset to 0
EPwm1Regs.DCFWINDOW = MIN_PERIOD; // Blanking window duration = MIN_CYCLE
// EPwm1Regs.DCFOFFSET = MAX_PERIOD-3; // Set filter offset to TBPRD-3 to compensate for 3 clock delay to start blanking window (wraps to next cycle)
// EPwm1Regs.DCFWINDOW = MIN_PERIOD+3; // Blanking window duration = MIN_CYCLE, plus 3 to compensate for starting window 3 clocks early.
// Action-Qualifier Submodule Registers
EPwm1Regs.AQCTLA.bit.ZRO = 3; // 3 = when counter = zero toggles EPWM1A output
EPwm1Regs.AQCTLA.bit.CAU = 0; // 0 = Do nothing (action disabled)
EPwm1Regs.AQCTLA.bit.PRD = 0; // 0 = Do nothing (action disabled)
EPwm1Regs.AQCTLB.bit.ZRO = AQ_NO_ACTION;
EPwm1Regs.AQCTLB.bit.CAU = AQ_NO_ACTION;
EPwm1Regs.AQCTLB.bit.PRD = AQ_NO_ACTION;
// Dead-Band Generator Submodule Registers
EPwm1Regs.DBCTL.bit.IN_MODE = 0; // 0 = EPWM1a input only
EPwm1Regs.DBCTL.bit.POLSEL = 2; // EPWM1b inverted
EPwm1Regs.DBCTL.bit.OUT_MODE = 3; // dead-band applied to both EPWM1a and EPWM1b outputs
EPwm1Regs.DBRED = RED; // sets the deadband timing
EPwm1Regs.DBFED = FED; // sets the deadband timing

// Configure EPWM4 to generate ISR and ramp generator PWMSYNC timings

// Time-Base Submodule Registers
EPwm4Regs.TBCTL.bit.PRDLD = TB_IMMEDIATE; // set Immediate load
EPwm4Regs.TBPRD = MAX_PERIOD-1; // PWM frequency = 1 / period
EPwm4Regs.TBCTR = 0;
EPwm4Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;
EPwm4Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1;
EPwm4Regs.TBCTL.bit.CLKDIV = TB_DIV1;
EPwm4Regs.TBCTL.bit.PHSEN = TB_ENABLE;
EPwm4Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
EPwm4Regs.TBPHS.half.TBPHS = Epwm4_Tbphs; // sets phase for EPWM4 on sync
// Counter-Compare Submodule Registers
EPwm4Regs.CMPA.half.CMPA = Epwm4_CmpA; // Sets EPWM4 output pulse start and trigger point for CNTL_ISR
EPwm4Regs.CMPB = 0; // set duty 0% initially
EPwm4Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;
EPwm4Regs.CMPCTL.bit.LOADAMODE = CC_CTR_PRD;
// Action-Qualifier Submodule Registers
EPwm4Regs.AQCTLA.bit.ZRO = 1; // 1 = output low
EPwm4Regs.AQCTLA.bit.CAU = 2; // 2 = output high
EPwm4Regs.AQCTLA.bit.PRD = 0; // 0 = Do nothing (action disabled)
EPwm4Regs.AQCTLB.bit.ZRO = AQ_NO_ACTION;
EPwm4Regs.AQCTLB.bit.CAU = AQ_NO_ACTION;
EPwm4Regs.AQCTLB.bit.PRD = AQ_NO_ACTION;
// High Resolution Period Control Register
EPwm4Regs.HRPCTL.bit.PWMSYNCSEL = 1; // PWMSYNC generated at EPWM4 TBCTR = 0 for synchronizing comparator ramp generators

// Configure the comparator and ramp generator blocks
Comp1Regs.COMPCTL.bit.SYNCSEL = 1; // Sync output with SYSCLK / use Qualification
Comp1Regs.COMPCTL.bit.QUALSEL = 4; // Qualification period = 4 clocks
Comp1Regs.COMPCTL.bit.CMPINV = 0; // Output High when true
Comp1Regs.COMPCTL.bit.COMPDACEN = 1; // Power up Comparator locally
Comp1Regs.COMPCTL.bit.COMPSOURCE = 0; // Connect the inverting input to internal DAC
Comp1Regs.COMPCTL.bit.QUALSEL = 3; // Comparator output must be active for 2 consecutive clocks before resetting the RAMP
Comp1Regs.DACVAL.bit.DACVAL = 0x3FF; // Set DAC output - Q10
Comp1Regs.DACCTL.bit.DACSOURCE = 1; // 0 - DACVAL; 1 - Internal ramp for slope compensation
Comp1Regs.DACCTL.bit.RAMPSOURCE = 3; // 3 = PMW4
Comp1Regs.RAMPDECVAL_SHDW = Slope; // Set initial slope

Comp2Regs.COMPCTL.bit.SYNCSEL = 1; // Sync output with SYSCLK / use Qualification
Comp2Regs.COMPCTL.bit.QUALSEL = 4; // Qualification period = 4 clocks
Comp2Regs.COMPCTL.bit.CMPINV = 0; // Output High when true
Comp2Regs.COMPCTL.bit.COMPDACEN = 1; // Power up Comparator locally
Comp2Regs.COMPCTL.bit.COMPSOURCE = 0; // Connect the inverting input to internal DAC
Comp2Regs.COMPCTL.bit.QUALSEL = 3; // Comparator output must be active for 2 consecutive clocks before resetting the RAMP
Comp2Regs.DACVAL.bit.DACVAL = 0x3FF; // Set DAC output - Convert to Q10
Comp2Regs.DACCTL.bit.DACSOURCE = 1; // 0 - DACVAL; 1 - Internal ramp for slope compensation
Comp2Regs.DACCTL.bit.RAMPSOURCE = 3; // 3 = PMW4
Comp2Regs.RAMPDECVAL_SHDW = Slope; // Set initial slope

EDIS;

Thanks,

Ciaran

Tommy,

Thanks for the clarifications.  It's a lot better than it first appeared!

>> Would you be able to use a single EPWM for both actuation and PWMSYNC generation by taking advantage of the RAMPDLY function?

>> The improved CMPSS + EPWM system enables additional flexibility for when PWMSYNC is generated.  Instead of only 0 or PRD, it is now possible to generate PWMSYNC on CMPC or CMPD match.

Those are nice features.  The additional flexibility of generating PWMSYNC using a counter compare during the blanking window would solve problem #1 (comparator doesn't trip so ramp generator doesn't reset).  The EPWMBLANK and RAMPDLY should solve my problem #2 (Comparator trips during blanking window so ramp generator resets but the EPWM doesn't).  

>> These synchronizers all use EPWMBLANK as a reset signal so they will also blank the ramp generator COMPSTS reset signal until EPWMBLANK is deasserted.

Excellent!  I missed the path from EPWMBLANK to the reset pin on the latch immediately following the comparator.  

I've found this sequence is necessary on the F28027 to avoid bad things at the boundaries:

1. TBCTR=0
2. Start EPWM blanking window
3. Toggle EPWM output (CMPA)
4. Switch comparator input to event filter (DCAHCOMPSEL)
5. Disable ramp generator for last phase (DACSOURCE=0, DACVAL = max value)
6. Force reset of ramp generator for this phase (DACSOURCE=1)
7. End EPWM blanking window
8. Start ramp generator for this phase (PWMSYNC from a second EPWM)

How is this accomplished with the CMPSS? My guess:

1. TBCTR=0
2. Start EPWM blanking window (same)
3. Start comparator blanking window (EPWMBLANK)
4. Toggle EPWM output (same)
5. Switch comparator input to event filter (same)
6. Force reset of ramp generator for this phase (EPWMSYNCPER, set by CMPC)
7. End EPWM blanking window (same)
8. End comparator blanking window (EPWMBLANK)
9. Start ramp generator for this phase (RAMPDLY)

Would this work?  I am worried about the relative timing of the EPWM blanking and the comparator blanking, that there would be race conditions.

>> "Control register bits to force (or prevent) a ramp generator reset by software."  Would you still consider this to be necessary with the above clarifications?

Not if the sequence I proposed above works.  It's still desirable though.  One of the powerful attributes of the C2000 is the ability to supplement the capabilities of the hardware with ISR code where necessary.  I think having hooks to do that in the CMPSS would add capability.

Ciaran Brennan said:

Would this work?  I am worried about the relative timing of the EPWM blanking and the comparator blanking, that there would be race conditions.

Yes, you have the correct understanding. The EPWMBLANK signal in the CMPSS is taken directly from the internal blanking logic of the EPWM. The blanking window for both modules will be synchronized by design.

Ciaran Brennan said:

Not if the sequence I proposed above works.  It's still desirable though.  One of the powerful attributes of the C2000 is the ability to supplement the capabilities of the hardware with ISR code where necessary.  I think having hooks to do that in the CMPSS would add capability.

We will take this into consideration. For now, it should still be possible to perform the DACSOURCE toggle as you had done on F2802x.