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TMS320F280041: TMS320F280041 one of two (3, 4) SDFM channels does not receive data

Part Number: TMS320F280041
Other Parts Discussed in Thread: AMC1035, AMC1106E05

Hi I have a project using TMS320F280041 and two Sigma-Delta Modulators (AMC1035 and AMC1106E05).
The AMC1035 is configured for Manchester mode. Both are clocked from PWM generated 10MHz clock (verified with scope):

    // pwm_period = 10 here, CPU is running at 100MHz

    EPWM_setPeriodLoadMode(epwm_base, EPWM_PERIOD_DIRECT_LOAD);
    EPWM_setTimeBasePeriod(epwm_base, pwm_period - 1); // set it to SDFM_CLOCK_OUT_HZ frequency
    EPWM_setTimeBaseCounter(epwm_base, 0);             // start at 0
    EPWM_setPhaseShift(epwm_base, 0);                  // no phase shift
    EPWM_setTimeBaseCounterMode(epwm_base, EPWM_COUNTER_MODE_UP); // up-down PWM
    EPWM_setClockPrescaler(epwm_base, EPWM_CLOCK_DIVIDER_1, EPWM_HSCLOCK_DIVIDER_1);

    EPWM_setCounterCompareValue(epwm_base, EPWM_COUNTER_COMPARE_A, pwm_period / 2);
    EPWM_setActionQualifierAction(epwm_base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_HIGH,
                                  EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
    EPWM_setActionQualifierAction(epwm_base, EPWM_AQ_OUTPUT_A, EPWM_AQ_OUTPUT_LOW,
                                  EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);

The D3 input is connected to the AMC1106E05 data output and configured as follows:

    #define GPIO_SDFM_IOUT_DATA (28)
    #define GPIO_SDFM_IOUT_DATA_PIN_CONFIG GPIO_28_SD_D3 
    
    // Sigma-Delta inputs (and clock)
    // Data Output Current
    GPIO_setDirectionMode(GPIO_SDFM_IOUT_DATA, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(GPIO_SDFM_IOUT_DATA, GPIO_PIN_TYPE_INVERT);
    GPIO_setQualificationMode(GPIO_SDFM_IOUT_DATA, GPIO_QUAL_ASYNC); 
    GPIO_setPinConfig(GPIO_SDFM_IOUT_DATA_PIN_CONFIG);

The D4 input is connected to the AMC1035 data output and configured as follows:

    #define GPIO_SDFM_VSEC_DATA (22)
    #define GPIO_SDFM_VSEC_DATA_PIN_CONFIG GPIO_22_SD_D4
    
    // Data output voltage
    GPIO_setDirectionMode(GPIO_SDFM_VSEC_DATA, GPIO_DIR_MODE_IN);
    GPIO_setPadConfig(GPIO_SDFM_VSEC_DATA, GPIO_PIN_TYPE_INVERT);
    GPIO_setQualificationMode(GPIO_SDFM_VSEC_DATA, GPIO_QUAL_ASYNC); 
    GPIO_setPinConfig(GPIO_SDFM_VSEC_DATA_PIN_CONFIG);

The SDFM channels are configured identically:

    #define SDFM_IOUT_FILTER SDFM_FILTER_3
    #define SDFM_VSEC_FILTER SDFM_FILTER_4
    
    SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD1);
    // Configure Input Control Unit: Modulator Clock rate = Modulator data rate
    // We have D3 (IOUT) and D4 (VSEC) machester coded (that is done by SDFM_MODULATOR_CLK_OFF)
    SDFM_setupModulatorClock(SDFM1_BASE, SDFM_IOUT_FILTER, SDFM_MODULATOR_CLK_OFF);
    SDFM_setupModulatorClock(SDFM1_BASE, SDFM_VSEC_FILTER, SDFM_MODULATOR_CLK_OFF);

    // Configure Data Filter Unit - filter type, OSR value and enable / disable data filter
    // SINC3 + OSR=32 gives resolution of exactly 16bit signed integer
    SDFM_configDataFilter(SDFM1_BASE, (SDFM_IOUT_FILTER | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(32)),
                          (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE | SDFM_SHIFT_VALUE(1)));
    SDFM_configDataFilter(SDFM1_BASE, (SDFM_VSEC_FILTER | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(32)),
                          (SDFM_DATA_FORMAT_16_BIT | SDFM_FILTER_ENABLE | SDFM_SHIFT_VALUE(1)));

    // Enable Master filter bit: Unless this bit is set none of the filter modules
    // can be enabled. All the filter modules are synchronized when master filter
    // bit is enabled after individual filter modules are enabled.
    SDFM_enableMasterFilter(SDFM1_BASE);

    SDFM_disableExternalReset(SDFM1_BASE, SDFM_IOUT_FILTER);
    SDFM_disableExternalReset(SDFM1_BASE, SDFM_VSEC_FILTER);

    SDFM_enableInterrupt(
        SDFM1_BASE, SDFM_IOUT_FILTER,
        (SDFM_MODULATOR_FAILURE_INTERRUPT | SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT));
    SDFM_enableInterrupt(
        SDFM1_BASE, SDFM_VSEC_FILTER,
        (SDFM_MODULATOR_FAILURE_INTERRUPT | SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT));
    SDFM_enableMasterInterrupt(SDFM1_BASE);


The problem us that the I get correct data from the channel 3, but nothing on channel 4.
Since I have enabled MF interrupt I get MF bit 1 on both channels..
If I clear them then it stays cleared on channel 3 and I get also AF bit set (as well as the expected data Current readout).
On the channel 4 the MF stays 1. I understood that it's lack of the clock.. but since both channels are machester coded it should not expect clock.

The interesting part is that if I swap data lines.. i.e. I put the signal that was on D3 to D4 and signal that was D4 to D3 I still get data only on D3 and I also get expected readout (in this case Voltage).
So in short the same data stream works on one channel but does not on the other (and vice versa).

It's also worth noting that I left the clock to be fed to GPIO_29 (i.e. SC3) but the GPIO pin is configured to be GPIO. And also both filters are configured to Mode 2.

    // make sure that SC3 is set to gpio
    GPIO_setPinConfig(GPIO_29_GPIO29);

Also if I check the configurations of SD3 and SD4 in the debugger while the code is running they are identical as well as the GPIO configuration of respective data inputs.
So I am puzzled as to why one of them is working and the other one does not...