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TMS320F2809: Filling SPI TX FIFO registers

Daniel Rush
Intellectual 585 points
Part Number: TMS320F2809
Other Parts Discussed in Thread: MOTORWARE

I am writing some code to interact with a external peripheral that uses a SPI-like communication. I give it a clock and it gives me data, so I'm using the peripheral as follows:

  1. Read the data in the SPI's RX FIFO
  2. Process data
  3. Fill Tx FIFO

This routine runs at 1khz in the SYS-BIOS. The problem is I run into traces that look like this: 

The gap on the top(CLK) trace causes the peripheral to time out and think that the next word is a new transaction.

This is what the code for filling the TX FIFO looks like:

  // Fill the FIFO to get new sample ready.
  for (int words_needed = 4; words_needed > 0; words_needed--) {
    spi_handle_->SPITXBUF = 0xFFFF;
    // Wait for buffer to empty
    while (SPI_getTxBufferStatus(spi_handle_) == SPI_TxBufferStatus_Full);
  }

This isn't atomic, so when interrupted, this filling process can be delayed. What I want to do is put a SPI_disableTx() before then SPI_enableTx() after, but for some reason when you disable TX it doesn't stop the peripheral from clocking which ruins this idea. 


Would love some help on this!

Thanks!

  • 0
    TI__Guru 55700 points

    Daniel,

    What device are you trying to interface SPI with? Are you trying to use F2809.SPI as master?

    How are you enabling / disabling transmit function? How are you using TX/RX FIFO?

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    Intellectual 585 points

    Hey Manoj!

    This is my entire setup for the SPI peripheral

      // Setup peripheral clock
  SPI_setClkPolarity(spi_handle_, SPI_ClkPolarity_OutputFallingEdge_InputRisingEdge);
  SPI_setClkPhase(spi_handle_, SPI_ClkPhase_Normal);
  // Set to master mode
  SPI_setMode(spi_handle_, SPI_Mode_Master);
  // Baud Rate = (SYSCLK / 12) / 7 = 1.07Mhz
  SPI_setBaudRate(spi_handle_, (SPI_BaudRate_e)0b111);
  SPI_setCharLength(spi_handle_, SPI_CharLength_16_Bits);
  SPI_disableLoopBack(spi_handle_);
  SPI_disableOverRunInt(spi_handle_);
  // Disable TX so that periph doesn't write to MOSI(pin is used for something else)
  SPI_disableTx(spi_handle_);
  // No TX delay as we're going to be doing larger than 16-bit writes back-to-back
  SPI_setTxDelay(spi_handle_, 0);
  // Setup FIFO level int
  SPI_resetRxFifo(spi_handle_);
  SPI_clearRxFifoInt(spi_handle_);
  SPI_setRxFifoIntLevel(spi_handle_, SPI_FifoLevel_4_Words);
  SPI_enableRxFifo(spi_handle_);

  • 0 in reply to Daniel Rush
    TI__Guru 55700 points

    Daniel,

    I'm not familiar with these functions? Are these your custom drivers?

    Also, which device are you trying to interface SPI?

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    TI__Guru 55700 points

    Are you using TX FIFO? Is your TX FIFO and RX FIFO levels are of same length.

    I don't see TX FIFO configuration in your code.

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    Intellectual 585 points

    Manoj,

    These are MotorWare drivers, from TI. The SPI Fifo word length is a single register that determines the length of the words transferred, controls RX and TX since they both pull from the same buffer in the peripheral. Using SPI-B peripheral, interfacing with an encoder that uses a SPI-Like interface. The problem is I cant fill the TX buffer while holding the SPI CLK in reset(TALK bit doesn't stop the clock from running, and the reset bit also resets the fifo so once I clear reset it resets the FIFO pointer.)

  • 0 in reply to Daniel Rush
    TI__Guru 55700 points

    Daniel,

    When you configure SPI as master, it provides SPICLK only when SPI transmits data. Once transmission of one word is complete, SPICLK shouldn't toggle like what you have shown.

    I would suggest you look into below SPI example code provided.

    C280x, C2801x C/C++ Header Files and Peripheral Examples

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    Intellectual 585 points

    I have it configured as a master, and as you can see, what you have said isn't true. It does toggle when when the TX bit is disabled. However I fixed it by moving the filling of the fifo into the interrupt that was interrupting the fifo fill so now there is nothing higher priority to interrupt it.