Vivek,
Thank you for your response to the previous thread.
In the previous thread we understood about connecting 1Mx16bit SRAM to the EMIF1_CS2n.
Then, my customer would like to add a 512Kx8bit SRAM to EMIF1_CS3n. Could you please advise again?
From the F28075 DS, p155: Table 6-3. EMIF Chip Select Memory Map
Q1.
My customer would like to connect a couple of asynchronous devices:
- EMIF1_CS2n: 1Mx16bit SRAM
- EMIF1_CS3n: 512Kx8bit SRAM
Q. Then, is it possible to add a 512Kx8bit SRAM to the EMIF1_CS3n and access whole the memory?
The table above doesn't show restrictions to CS3. I found no concerns, but I would like to make sure.
Q2.
We would expect the following address translation.
Could you please tell me if any concerns ?
From my previous thread, I modified the yellow cells for CS3n.
