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TMS320F28021: SPI and SCI Communication Synchronisation.

Part Number: TMS320F28021

Hello Team,

Background:

I'm using TMS320F28021 chip to communicate with some ASICs via SPI(1 Mbps) port and another controller with SCI port (converted to RS485 at 115kbps).

Issue:

For the SPI communication, the case is similar to the senario in this thread --> https://e2e.ti.com/support/microcontrollers/c2000/f/171/t/655436

To get a reply from the ASIC I send some dummy data (to generate clock for SPI slave) and wait until I receive the whole data.

THe problem is, this wait time will coincide with the SCI receive.

Currently, I implemented these two options:

  1. Disable the SCI Rx interrupts while SPI receive is in progress.
    1. This will result is loosing relevant information from the master and the master should send the message again hence increasing the total acqusation time.
  2. Ignore the SPI data if it is interrupted by the SCI Rx.
    1. This will result in a lot of reconfiguring time for the ASIC.

I can somehow manage with these two options but not the ideal solutions. So Is there any other option where the SPI peripheral handles the clocks itself instead of an active assertion form the application?

  • Anudeep,

    Unfortunately, you don't have DMA / CLA to offload some task to secondary masters on this device. So, the only option you have are the FIFOs available in both SCI and SPI. I hope you are already using FIFOs in corresponding peripheral to reduce the frequency of SCI / SPI interrupts. If so, there isn't much we can do other than time when SCI and SPI communicates.

    Regards,

    Manoj