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TMS320F28335: How to detect a SCI TX data completion for RS485 DE/RE control?

Steve Lim
Intellectual 2745 points
Part Number: TMS320F28335

Hi Champs,

My one customer faced one issue while using SCI with FIFO mode for RS485 interface.

They have been using SCI TX_EMPTY flag for checking of transmit completion like the below figure in datasheet.

It usually seemed to work well. But TX_EMPTY flag get active intermittently before STOP bit is transmitted completely.

Q1) What is the cause of the problem? 

Q2) Do you have some guidance for correctly using DE and RE in RS485?

Thanks,

Steve

  • 0
    TI__Genius 17315 points

    Steve,

    As you may know, the F28335 SCI uses RS-232 type communication.  The two communication standards (RS-232 and RS485) are not compatible.  Do you know if they are using adapters to convert between the two standards?

    From past experience, I will try a "best guess" on why the TX EMPTY is occurring immediately before the Stop bit is completed.  There are eight SCICLK periods per data bit.  The TX EMPTY signal might be getting active a few SCICLK cycles before (e.g. 5/8 of a bit time).  This might have been done in the design for internal synchronize reasons.  Again, a "best guess" based on a timing question related to the BRKDT flag (which occurs 9.625 bit periods, and not 10 bit periods, following a missing stop).  If needed, I will have the design team investigate and confirm.

    I hope this helps. If this answers your question, please click the green "Verified Answer" button. Thanks.

    - Ken

  • 0 in reply to Ken Schachter
    TI__Intellectual 2745 points

    Hi Ken,

    Thank you for your quick answer.

    They are using external RS485 transceiver.  They added some delay after TM EMPTY flag to solve the issue now. I think your answer might help them to check the delay timing.

    Thanks,

    Steve