My customer would like to use a timer ISR function (@1sec) and read the latest EcapxRegs.CAPy value.
We are afraid that a race condition between a CPU read and a EcapxRegs.CAPy update, because the CPU read is not synchronized to Ecap events.
We are afraid to read a wrong or not properly updated value from the register.
Q1. Could you please advise whether the race condition possible?
Q2. If yes, could you please advise its solution? I wonder that CAPLDEN bit would work.