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TMS320F280025C: Device pin handling

Koichiro Tashiro
Mastermind 22945 points

Part Number: TMS320F280025C

Hi,

I have a few questions from my customer who is designing their own board now.

Q1) VDD decoupling capacitors:
According to datasheet,
“TI recommends placing a decoupling capacitor near each VDD pin with a total capacitance of approximately 22 μF.”
Customer wants to make sure each VDD pin needs to be connected together or not.
If not, how the 22uF should be distributed for each VDD pin?
ex. Suppose 48 QFP, there are two VDD pins. 2uF for one pin and 20uF for another pin is acceptable?

Q2) Unused AIO pins:
It is not clear how to handle unused AIO pins. They are not listed in datasheet Table 4-9.
Is this OK to connect VSS?

Q3) VREFHI pin usage:
In case internal reference is used, adding 2.2uF capacitor is enough, right?

Thanks and regards,
Koichiro Tashiro

 

  • 0
    TI__Guru 60865 points

    Hi Tashiro-san,

    1) You can connect the VDD pins externally if desired.  If you don't connect the pins, then we would recommend relatively balanced capacitance between the pins (say 10uF on one VDD, 12uF on the other VDD).  If you do connect the pins externally, you could distribute the capacitance as desired among 2 or more capacitors, but still put at least one capacitor close to each pin (for example, 1uF close to each pin, then two more 10uF capacitors somewhere on the connected VDD net).     

    2) All unused AIO pins would also be unused ADC/analog pins, so follow the directions for unused analog channels. 

    3)Yes, just place a 2.2uF capacitor on the VREFHI pin. 

    (Note: In the case of C2000 devices with multiple VREFHI pins and internal reference mode - for example F28004x - you would put a 2.2uF capacitor on each pin but do NOT connect the VREFHI pins together because each VREF has an independent driver that could result in contention if connected). 

  • 0 in reply to Devin Cottier
    TI__Mastermind 22945 points

    Hi Devin,

    Sorry for my late reply.
    I understood #1 and #3.

    For #2, there seems no analog channels other than VREFHI/LO in datasheet Table 4-9.
    Could you point me which “directions” should be followed?

    Thanks and regards,
    Koichiro Tashiro

  • 0 in reply to Koichiro Tashiro
    TI__Guru 60865 points

    Hi Tashiro-san,

    It looks like we are missing the instructions for analog pins in the F28002x family datasheet.  I'll submit a ticket to have this corrected.

    In the meantime, the instructions will be the same as F28004x devices without PGA out or DAC out: