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CCS/TMS320F28388D: when the queue is empty, SPI interrupts are constantly called

Part Number: TMS320F28388D
Other Parts Discussed in Thread: C2000WARE

Tool/software: Code Composer Studio

Hello!!!

we have purchased the following set of development boards:
1. HSEC180 controlCARD Baseboard Docking Station
www.ti.com/.../TMDSHSECDOCK
2.F28388D controlCARD evaluation module
www.ti.com/.../TMDSCNCD28388D

now I have created a test project based on the examples that come with C2000Ware_3_02_00_00 for this controller, in it I want to do the following: transmit data via SPI, seeing that the interrupt is being triggered and the counter of transmitted packets is increasing, stand up with an oscillator on the pins and see the clock and data

void Test_Dev_Init(void){   
    //SPI_A
    pin = 18; // CLK
    GPIO_setMasterCore(pin, GPIO_CORE_CPU1);
    GPIO_setPinConfig(GPIO_18_SPIA_CLK);
    GPIO_setPadConfig(pin, GPIO_PIN_TYPE_PULLUP);
    GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
    pin = 16; //SIMO
    GPIO_setMasterCore(pin, GPIO_CORE_CPU1);
    GPIO_setPinConfig(GPIO_16_SPIA_SIMO);
    GPIO_setPadConfig(pin, GPIO_PIN_TYPE_PULLUP);
    GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
    pin = 17; //SOMI
    GPIO_setMasterCore(pin, GPIO_CORE_CPU1);
    GPIO_setPinConfig(GPIO_17_SPIA_SOMI);
    GPIO_setPadConfig(pin, GPIO_PIN_TYPE_PULLUP);
    GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
    pin = 19; // STE
    GPIO_setMasterCore(pin, GPIO_CORE_CPU1);
    GPIO_setPinConfig(GPIO_19_SPIA_STEN);
    GPIO_setPadConfig(pin, GPIO_PIN_TYPE_PULLUP);
    GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC);
    //CONFIGURATION
    SPI_disableModule(SPIA_BASE);
    // SPI configuration. Use a 500kHz SPICLK and 16-bit word size.
    SPI_setConfig(SPIA_BASE, DEVICE_LSPCLK_FREQ, SPI_PROT_POL0PHA0, SPI_MODE_MASTER, SPI_A_SPEED, SPI_A_DATA_WIDTH);
    SPI_disableLoopback(SPIA_BASE);
    SPI_setEmulationMode(SPIA_BASE, SPI_EMULATION_FREE_RUN);
    // FIFO and interrupt configuration
    SPI_enableFIFO(SPIA_BASE);
    SPI_resetTxFIFO(SPIA_BASE);
    SPI_setFIFOInterruptLevel(SPIA_BASE, SPI_FIFO_TX8, SPI_FIFO_RX8);
    SPI_clearInterruptStatus(SPIA_BASE, SPI_INT_TXFF);
    SPI_enableInterrupt(SPIA_BASE, SPI_INT_TXFF);
    SPI_enableModule(SPIA_BASE);

    Interrupt_register(INT_SPIA_TX, &SPI_A_FIFO_ISR);
    Interrupt_enable(INT_SPIA_TX);
}

///////////////////          TEST SPI            /////////////////////////
volatile uint16_t spi_txMsgCount = 0;

__interrupt void SPI_A_FIFO_ISR(void){
    uint32_t i,status;

    status = SPI_getInterruptStatus(SPIA_BASE);
    i = SPI_getTxFIFOStatus(SPIA_BASE);
    SCIprintf("\r\nSPI_A_FIFO_ISR(int_sts = 0x%x,fifo_sts = 0x%x,)",status,i);

    spi_txMsgCount++;

    SPI_clearInterruptStatus(SPIA_BASE, SPI_INT_TXFF);
    Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP6);

    status = SPI_getInterruptStatus(SPIA_BASE);
    i = SPI_getTxFIFOStatus(SPIA_BASE);
    SCIprintf("\r\nSPI_A_FIFO_ISR_AFTER(int_sts = 0x%x,fifo_sts = 0x%x,)",status,i);

}

void Test_Dev_SPI(void){
    uint32_t i;
    uint16_t spi_data[2] = {0,0};

    SCIprintf("\r\nTest_Dev_SPI Start");
    while(spi_txMsgCount < 10){
        for(i = 0; i < 2; i++)  {
           SPI_writeDataNonBlocking(SPIA_BASE, spi_data[i] << (16 - SPI_A_DATA_WIDTH));
           spi_data[i]++;
        }
    }

    SCIprintf("\r\nTest_Dev_SPI End");
}

void main(void)
{   // Initialize device clock and peripherals
    Device_init();

    // Boot CM core
#ifdef _FLASH
    Device_bootCM(BOOTMODE_BOOT_TO_FLASH_SECTOR0);
#else
    Device_bootCM(BOOTMODE_BOOT_TO_S0RAM);
#endif

    // Initialize GPIO
    Device_initGPIO();

    // Disable CPU interrupts
    DINT;

    // Initialize interrupt controller and vector table.
    Interrupt_initModule();
    Interrupt_initVectorTable();
    IER = 0x0000;
    IFR = 0x0000;

    //init interface and periphery
    Test_Dev_Init();


    EINT;
    ERTM;

    SCIprintf("\033c");
    SCIprintf("\r\n|||||||||||||||||||||||||||||||||||||||\n");


    Test_Dev_SPI();

}



now I see the following: by SPI, as soon as I enable the interrupt, an SPI interrupt is immediately called, although data was not transmitted via SPI, while the transmission flag is not cleared, as can be seen from the debug print:

SPI_A_FIFO_ISR (int_sts = 0x8, fifo_sts = 0x0,)
SPI_A_FIFO_ISR_AFTER (int_sts = 0x8, fifo_sts = 0x0,)
SPI_A_FIFO_ISR (int_sts = 0x8, fifo_sts = 0x0,)
SPI_A_FIFO_ISR_AFTER (int_sts = 0x8, fifo_sts = 0x0,)
SPI_A_FIFO_ISR (int_sts = 0x8, fifo_sts = 0x0,)
SPI_A_FIFO_ISR_AFTER (int_sts = 0x8, fifo_sts = 0x0,)
SPI_A_FIFO_ISR (int_sts = 0x8, fifo_sts = 0x0,)
SPI_A_FIFO_ISR_AFTER (int_sts = 0x8, fifo_sts = 0x0,)
SPI_A_FIFO_ISR (int_sts = 0x8, fifo_sts = 0x0,)
SPI_A_FIFO_ISR_AFTER (int_sts = 0x8, fifo_sts = 0x0,)
SPI_A_FIFO_ISR (int_sts = 0x8, fifo_sts = 0x0,)
SPI_A_FIFO_ISR_AFTER (int_sts = 0x8, fifo_sts = 0x0,)
SPI_A_FIFO_ISR (int_sts = 0x8, fifo_sts = 0x0,)
SPI_A_FIFO_ISR_AFTER (int_sts = 0x8, fifo_sts = 0x0,)
SPI_A_FIFO_ISR (int_sts = 0x8, fifo_sts = 0x0

most likely the matter is in setting up the interrupts themselves, but I reviewed everything according to the examples, I did it right, and the examples themselves behave the same

I ask you to look at the initialization, maybe you will have some ideas, I have already reviewed a bunch of examples from TI, on github, I did not see what could be the reason for working out interrupts via SPI in this way

I would also like to draw your attention to the fact that the module is powered through an external power supply + 5V, 1.2A, i.e. the current should be enough

  • Dsd,

    Based on your code, you have enabled SPI TX FIFO interrupt (TXFFINT). SPI TX FIFO interrupt gets generated whenever TXFFST <= TXFFIL. Based on your configuration, TXFFIL = 8 and TXFFST will always be less than 8 (because you aren't writing more than 2 words), this means SPI TX FIFO interrupt keeps getting triggered which is the reason why you go into SPI_A_FIFO_ISR interrupt service routine again and again.

    Inside your SPI_A_FIFO_ISR, you are reading and storing SPISTS register contents in int_sts and TXFFST value in fifo_sts. There were couple of issues here.

    1) Clearing TXFFINT flag doesn't have any effect on TXFFST value.

    2) When TXFFINT flag is cleared, it sets itself again because TXFFST is still less than TXFFIL. If you want to properly clear TXFFINT flag, make sure to fill the SPI TX FIFO so that TXFFST > TXFFIL (8) and then clearn TXFFINT flag.

    I also get a feel that you should be reading and storing the TXFFST in your ISR, you be the reading the status of TXFFINT flag bit and store it.

    Regards,

    Manoj