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TMS320F28379D: GPIO interrupt with SYS/BIOS

Part Number: TMS320F28379D

Hello,

I am unable to configure my F28379D to generate ISR at rising edge of GPIO23, please review code snippets below, thanks:

CPU01_main.c

/* GPIO23 Interrupt from Altera */
GPIO_setDirectionMode(23 ,GPIO_DIR_MODE_IN);
GPIO_setQualificationMode(23, GPIO_QUAL_SYNC);
GPIO_setMasterCore(23, GPIO_CORE_CPU2);

CPU02_main.c

/*
 * Configure ALTERA(FPGA) to DSP interrupt line
 */
void AlteraInerruptCfg()
{
    /* Enable X-INT interrupt in the PIE: Group 1 interrupt 4 */
    Interrupt_enable(INT_XINT1);

    /* Set Interrupt GPIO */
    GPIO_setInterruptPin(23, GPIO_INT_XINT1);

    /* Edge type interrupt */
    GPIO_setInterruptType(GPIO_INT_XINT1, GPIO_INT_TYPE_RISING_EDGE);

    /* Enable XINT1 */
    GPIO_enableInterrupt(GPIO_INT_XINT1);
}

my cfg file:

/* ================ Hwi configuration ================ */
//var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
var c28Hwi = xdc.useModule('ti.sysbios.family.c28.Hwi');
/*
 * Create Hwi instances for PIE.
 *
 * Using the mappings found in the table "PIE MUXed Peripheral Interrupt Vector
 * Table" (found in the SYS/BIOS API Documentation), the following mappings for
 * interrupt number can be found:
 *
 *  PIE group 1, interrupt 4 -> interrupt number 35 -> XINT1 interrupt
 *
 *
 * Both PIE interrupts are also configured to run the interrupt service routine
 * 'myIsr()' when triggered.
 */


/* PIE group 1, interrupt 4 */
var interruptNum = 35;
var hwiParams = new c28Hwi.Params();
hwiParams.arg = interruptNum;
hwiParams.enableAck = true;
hwiParams.maskSetting = c28Hwi.MaskingOption_BITMASK;
hwiParams.disableMask = 0x0;
hwiParams.restoreMask = 0x0;
c28Hwi.create(interruptNum, "&xint1_isr", hwiParams);

  • Hello,

    I suspect the call to Interrupt_enable() is corrupting your Hwi instance. The interrupt is configured purely via the Hwi module. The only responsibility of your application is to configure the GPIO peripheral's interrupt registers.

    Derrick

  • Hi Derrick,

    I don't think that this is the issue because when I "manually" set the appropriate flag in PIEIFR1 register the ISR is executed.

    Thanks

  • I've tried with different GPIO (GPIO42) and still not getting ISR to execute at rising edge....

  • Zvi,

    Can you explain what the Interrupt_enable() API does?

    You can certainly configure interrupts around the RTOS--similar to what would be done in a bare metal application; however, this behavior would be incorrect. When using a RTOS, it must be aware of all interrupts. Similarly, all interrupts must be configured solely through the RTOS. Failure to do this may corrupt the scheduler and application.

    If the Interrupt_enable() API solely modifies the GPIO peripherals interrupt register, then there is no issue. But the Interrupt_enable() register may be overwriting what the RTOS has already done due to the Hwi instance created.

    Additionally, you may consider configuring your interrupt during runtime with the Hwi module to help debug. This would require you to use Hwi_create() from within your application.

    Regards,
    Derrick

  • Hi Derrick,

    I've removed the  Interrupt_enable(), it did not helped the main goal to get interrupt on core2 for rising edge of GPIO23

    Thank you

  • Zvi,

    From what I can tell, your Hwi configuration is correct and I'd expect you'd get interrupts without issue.

    Is there anything unusual about this specific use case? Have you gotten any other GPIO interrupts to work? Perhaps other peripherals?

    Derrick

  • Hi,

    I have other peripherals generate interrupts:

    1. SPI-C DMA Channels 5 and 6

    2. SCI-C RX and TX interrupts

    3. I2C interrupts

    But no interrupts for GPIOs (I've tried GPIO23 and GPIO42)

    Edit 1:

    Tried the C200Ware driverlib example code and it works as expected ...

    Edit 2:

    2.1 Disabled everything but one task and GPIO interrupt and still did not work.

    2.2 Created a project from scratch that has one task and GPIO interrupt - works only on Core1 but not Core2 !!

    Best regards

  • I've solved this problem by moving all GPIO related configurations to Core1