Tool/software: TI C/C++ Compiler
Hello,
TI C2000 microcontrollers enable interrupt service routine to be re-entrant by software interrupt prioritization.
The problem I'm related with is the mechanism doesn't work sometimes.
Here's the short description and I attach the full source code so that you can reproduce the phenomenon.
There are 4 interrupts running and the highest priority is given to the SEQ1 interrupt which belongs to group 1 in PIE.
The service routine linked to SEQ1 interrupt is ADC_ISR(). And the other interrupt in group 1 is timer 1 interrupt for which SWT_250US_ISR() is made.
In ADC_ISR(), wTestISR7 increases by 1 in the first part and set to zero in the last part. wTestISR8 increases only when ADC_ISR() re-executes before it completes.
In the experiment wTestISR8 increases randomly by about 5 in 30 minutes. The result may vary.
The compiler version is C2000 Code Generation Tools 4.1.3.
The build option is as follows.
; Code Composer Project File, Version 2.0 (do not modify or remove this line)
[Project Settings]
ProjectDir="D:\project\2020\30. Issue Technology\10. PM VF\30. SW\02. S100\minimal_project_long_long_test\"
ProjectType=Executable
CPUFamily=TMS320C28XX
Tool="Compiler"
Tool="CustomBuilder"
Tool="DspBiosBuilder"
Tool="Linker"
Config="Debug"
Config="Release"
[Source Files]
Source="Boot.asm"
Source="Debug_Serial.c"
Source="DSP280x_Entry.asm"
Source="DSP280x_GlobalVariableDefs.c"
Source="DSP280x_SysCtrl.c"
Source="DSP280x_usDelay.asm"
Source="Lib\IQmath.lib"
Source="Lib\rts2800_ml.lib"
Source="Lib\SFO_TI_Build.lib"
Source="Main.C"minimal_project_long_long_test_ADCONV2.zip
Source="F2809_Start.cmd"
["Compiler" Settings: "Debug"]
Options=--preproc_only -pds9 -fr"$(Proj_dir)\Debug" -fs"$(Proj_dir)\Debug" -i"$(Proj_dir)\Include(TI)" -d"_DEBUG" -d"LARGE_MODEL" -ml -mt -v28
["Compiler" Settings: "Release"]
Options=-g -fr"$(Proj_dir)\Release" -d"_DEBUG" -d"LARGE_MODEL" -ml -v28
["Linker" Settings: "Debug"]
Options=-c -heap0x2000 -m".\Debug\ALLGrp_S100_Main.map" -o".\Debug\ALLGrp_S100_Main.out" -stack0x400 -w -x
["Linker" Settings: "Release"]
Options=-c -m".\Release\ALLGrp_S100_Main.map" -o".\Release\ALLGrp_S100_Main.out" -w -x
["test1.c" Settings: "Debug"]
Options="Compiler" +{-ppa -ppc -k}
["F2809_Start.cmd" Settings: "Debug"]
LinkOrder=1
interrupt void ADC_ISR(void)
{
Uint16 nCh;
Uint16 *pStartAddr;
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
IER |= 0x0001;
IER &= (0xFFFF & ~(1 << 1) & ~(1 << 2) & ~(1 << 3) & ~(1 << 4) & ~(1 << 5) & ~(1 << 6) & ~(1 << 7) & ~(1 << 8) & ~(1 << 9) & ~(1 << 10) & ~(1 << 11) & ~(1 << 12) & ~(1 << 13) & ~(1 << 14) & ~(1 << 15));
PieCtrlRegs.PIEIER1.all &= (0x00FE & ~(1 << 1) & ~(1 << 2) & ~(1 << 3) & ~(1 << 4) & ~(1 << 5) & ~(1 << 6) & ~(1 << 7));
PieCtrlRegs.PIEACK.all = 0xFFFF;
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1;
AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;
wTestISR7++;
wTestISR9 = EPwm4Regs.TBCTR;
if(wTestISR7 > 1) {
wTestISR8++;
wTestISR10 = wTestISR9;
}
asm(" clrc INTM");
pStartAddr = (Uint16 *)&(AdcRegs.ADCRESULT0);
for(nCh = 0; nCh < 3; nCh++) {
*adTbl[nCh].ch1 = (*(pStartAddr + nCh*2));
*adTbl[nCh].ch2 = (*(pStartAddr + nCh*2 + 1));
}
iIasAD = (SWORD)((WORD)wIasADRaw - (WORD)((WORD)(0x8000)));
iIbsAD = (SWORD)((WORD)wIbsADRaw - (WORD)((WORD)(0x8000)));
iIcsAD = (SWORD)((WORD)wIcsADRaw - (WORD)((WORD)(0x8000)));
asm(" setc INTM");
asm(" SETC OVM ");;
if(fSecondGroup == 0) {
iIas = iDirOfCT * ((((SLONG)iIasAD << 16) - ((SLONG)iIasOffset << 16)) >> 16);
iIbs0 = iDirOfCT * ((((SLONG)iIbsAD << 16) - ((SLONG)iIbsOffset << 16)) >> 16);
iIcs = iDirOfCT * ((((SLONG)iIcsAD << 16) - ((SLONG)iIcsOffset << 16)) >> 16);
iIbs = -((SLONG)iIas + iIcs);
}
wADConvCompleted = 1;
wADConvCntADISR++;
asm(" CLRC OVM ");;
asm(" clrc INTM");
wTestISR7 = 0;
asm(" setc INTM");
PieCtrlRegs.PIEIER1.all = TempPIEIER;
}
interrupt void SWT_250US_ISR(void)
{
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
IER |= 0x0001;
IER &= (0xFFFF & ~(1 << 1) & ~(1 << 2) & ~(1 << 3) & ~(1 << 4) & ~(1 << 5) & ~(1 << 6) & ~(1 << 7) & ~(1 << 8) & ~(1 << 9) & ~(1 << 10) & ~(1 << 11) & ~(1 << 12) & ~(1 << 13) & ~(1 << 14) & ~(1 << 15));
PieCtrlRegs.PIEIER1.all &= (0xFFFF & ~(1 << 1) & ~(1 << 2) & ~(1 << 3) & ~(1 << 4) & ~(1 << 5) & 0x00BF & ~(1 << 7));
PieCtrlRegs.PIEACK.all = 0xFFFF;
asm(" clrc INTM");
wTest5++;
asm(" setc INTM");
PieCtrlRegs.PIEIER1.all = TempPIEIER;
}
The preprocessed for main.c is as follows.
-------------------------------------------------
extern cregister volatile unsigned int IFR;
extern cregister volatile unsigned int IER;
typedef int int16;
typedef long int32;
typedef unsigned int Uint16;
typedef unsigned long Uint32;
typedef float float32;
typedef long double float64;
struct ADCTRL1_BITS {
Uint16 rsvd1:4;
Uint16 SEQ_CASC:1;
Uint16 SEQ_OVRD:1;
Uint16 CONT_RUN:1;
Uint16 CPS:1;
Uint16 ACQ_PS:4;
Uint16 SUSMOD:2;
Uint16 RESET:1;
Uint16 rsvd2:1;
};
union ADCTRL1_REG {
Uint16 all;
struct ADCTRL1_BITS bit;
};
struct ADCTRL2_BITS {
Uint16 EPWM_SOCB_SEQ2:1;
Uint16 rsvd1:1;
Uint16 INT_MOD_SEQ2:1;
Uint16 INT_ENA_SEQ2:1;
Uint16 rsvd2:1;
Uint16 SOC_SEQ2:1;
Uint16 RST_SEQ2:1;
Uint16 EXT_SOC_SEQ1:1;
Uint16 EPWM_SOCA_SEQ1:1;
Uint16 rsvd3:1;
Uint16 INT_MOD_SEQ1:1;
Uint16 INT_ENA_SEQ1:1;
Uint16 rsvd4:1;
Uint16 SOC_SEQ1:1;
Uint16 RST_SEQ1:1;
Uint16 EPWM_SOCB_SEQ:1;
};
union ADCTRL2_REG {
Uint16 all;
struct ADCTRL2_BITS bit;
};
struct ADCASEQSR_BITS {
Uint16 SEQ1_STATE:4;
Uint16 SEQ2_STATE:3;
Uint16 rsvd1:1;
Uint16 SEQ_CNTR:4;
Uint16 rsvd2:4;
};
union ADCASEQSR_REG {
Uint16 all;
struct ADCASEQSR_BITS bit;
};
struct ADCMAXCONV_BITS {
Uint16 MAX_CONV1:4;
Uint16 MAX_CONV2:3;
Uint16 rsvd1:9;
};
union ADCMAXCONV_REG {
Uint16 all;
struct ADCMAXCONV_BITS bit;
};
struct ADCCHSELSEQ1_BITS {
Uint16 CONV00:4;
Uint16 CONV01:4;
Uint16 CONV02:4;
Uint16 CONV03:4;
};
union ADCCHSELSEQ1_REG{
Uint16 all;
struct ADCCHSELSEQ1_BITS bit;
};
struct ADCCHSELSEQ2_BITS {
Uint16 CONV04:4;
Uint16 CONV05:4;
Uint16 CONV06:4;
Uint16 CONV07:4;
};
union ADCCHSELSEQ2_REG{
Uint16 all;
struct ADCCHSELSEQ2_BITS bit;
};
struct ADCCHSELSEQ3_BITS {
Uint16 CONV08:4;
Uint16 CONV09:4;
Uint16 CONV10:4;
Uint16 CONV11:4;
};
union ADCCHSELSEQ3_REG{
Uint16 all;
struct ADCCHSELSEQ3_BITS bit;
};
struct ADCCHSELSEQ4_BITS {
Uint16 CONV12:4;
Uint16 CONV13:4;
Uint16 CONV14:4;
Uint16 CONV15:4;
};
union ADCCHSELSEQ4_REG {
Uint16 all;
struct ADCCHSELSEQ4_BITS bit;
};
struct ADCTRL3_BITS {
Uint16 SMODE_SEL:1;
Uint16 ADCCLKPS:4;
Uint16 ADCPWDN:1;
Uint16 ADCBGRFDN:2;
Uint16 rsvd1:8;
};
union ADCTRL3_REG {
Uint16 all;
struct ADCTRL3_BITS bit;
};
struct ADCST_BITS {
Uint16 INT_SEQ1:1;
Uint16 INT_SEQ2:1;
Uint16 SEQ1_BSY:1;
Uint16 SEQ2_BSY:1;
Uint16 INT_SEQ1_CLR:1;
Uint16 INT_SEQ2_CLR:1;
Uint16 EOS_BUF1:1;
Uint16 EOS_BUF2:1;
Uint16 rsvd1:8;
};
union ADCST_REG {
Uint16 all;
struct ADCST_BITS bit;
};
struct ADCREFSEL_BITS {
Uint16 rsvd1:14;
Uint16 REF_SEL:2;
};
union ADCREFSEL_REG {
Uint16 all;
struct ADCREFSEL_BITS bit;
};
struct ADCOFFTRIM_BITS{
int16 OFFSET_TRIM:9;
Uint16 rsvd1:7;
};
union ADCOFFTRIM_REG{
Uint16 all;
struct ADCOFFTRIM_BITS bit;
};
struct ADC_REGS {
union ADCTRL1_REG ADCTRL1;
union ADCTRL2_REG ADCTRL2;
union ADCMAXCONV_REG ADCMAXCONV;
union ADCCHSELSEQ1_REG ADCCHSELSEQ1;
union ADCCHSELSEQ2_REG ADCCHSELSEQ2;
union ADCCHSELSEQ3_REG ADCCHSELSEQ3;
union ADCCHSELSEQ4_REG ADCCHSELSEQ4;
union ADCASEQSR_REG ADCASEQSR;
Uint16 ADCRESULT0;
Uint16 ADCRESULT1;
Uint16 ADCRESULT2;
Uint16 ADCRESULT3;
Uint16 ADCRESULT4;
Uint16 ADCRESULT5;
Uint16 ADCRESULT6;
Uint16 ADCRESULT7;
Uint16 ADCRESULT8;
Uint16 ADCRESULT9;
Uint16 ADCRESULT10;
Uint16 ADCRESULT11;
Uint16 ADCRESULT12;
Uint16 ADCRESULT13;
Uint16 ADCRESULT14;
Uint16 ADCRESULT15;
union ADCTRL3_REG ADCTRL3;
union ADCST_REG ADCST;
Uint16 rsvd1;
Uint16 rsvd2;
union ADCREFSEL_REG ADCREFSEL;
union ADCOFFTRIM_REG ADCOFFTRIM;
};
struct ADC_RESULT_MIRROR_REGS
{
Uint16 ADCRESULT0;
Uint16 ADCRESULT1;
Uint16 ADCRESULT2;
Uint16 ADCRESULT3;
Uint16 ADCRESULT4;
Uint16 ADCRESULT5;
Uint16 ADCRESULT6;
Uint16 ADCRESULT7;
Uint16 ADCRESULT8;
Uint16 ADCRESULT9;
Uint16 ADCRESULT10;
Uint16 ADCRESULT11;
Uint16 ADCRESULT12;
Uint16 ADCRESULT13;
Uint16 ADCRESULT14;
Uint16 ADCRESULT15;
};
extern volatile struct ADC_REGS AdcRegs;
extern volatile struct ADC_RESULT_MIRROR_REGS AdcMirror;
struct DEVICECNF_BITS {
Uint16 rsvd1:3;
Uint16 VMAPS:1;
Uint16 rsvd2:1;
Uint16 XRSn:1;
Uint16 rsvd3:10;
Uint16 rsvd4:3;
Uint16 ENPROT:1;
Uint16 MONPRIV:1;
Uint16 rsvd5:1;
Uint16 EMU0SEL:2;
Uint16 EMU1SEL:2;
Uint16 rsvd6:6;
};
union DEVICECNF_REG {
Uint32 all;
struct DEVICECNF_BITS bit;
};
struct PARTID_BITS {
Uint16 PARTNO:8;
Uint16 PARTTYPE:8;
};
union PARTID_REG {
Uint16 all;
struct PARTID_BITS bit;
};
struct DEV_EMU_REGS {
union DEVICECNF_REG DEVICECNF;
union PARTID_REG PARTID;
Uint16 REVID;
Uint16 PROTSTART;
Uint16 PROTRANGE;
Uint16 rsvd2[202];
};
extern volatile struct DEV_EMU_REGS DevEmuRegs;
struct TCR_BITS {
Uint16 rsvd1:4;
Uint16 TSS:1;
Uint16 TRB:1;
Uint16 rsvd2:4;
Uint16 SOFT:1;
Uint16 FREE:1;
Uint16 rsvd3:2;
Uint16 TIE:1;
Uint16 TIF:1;
};
union TCR_REG {
Uint16 all;
struct TCR_BITS bit;
};
struct TPR_BITS {
Uint16 TDDR:8;
Uint16 PSC:8;
};
union TPR_REG {
Uint16 all;
struct TPR_BITS bit;
};
struct TPRH_BITS {
Uint16 TDDRH:8;
Uint16 PSCH:8;
};
union TPRH_REG {
Uint16 all;
struct TPRH_BITS bit;
};
struct TIM_REG {
Uint16 LSW;
Uint16 MSW;
};
union TIM_GROUP {
Uint32 all;
struct TIM_REG half;
};
struct PRD_REG {
Uint16 LSW;
Uint16 MSW;
};
union PRD_GROUP {
Uint32 all;
struct PRD_REG half;
};
struct CPUTIMER_REGS {
union TIM_GROUP TIM;
union PRD_GROUP PRD;
union TCR_REG TCR;
Uint16 rsvd1;
union TPR_REG TPR;
union TPRH_REG TPRH;
};
struct CPUTIMER_VARS {
volatile struct CPUTIMER_REGS *RegsAddr;
Uint32 InterruptCount;
float CPUFreqInMHz;
float PeriodInUSec;
};
void InitCpuTimers(void);
void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period);
extern volatile struct CPUTIMER_REGS CpuTimer0Regs;
extern struct CPUTIMER_VARS CpuTimer0;
extern volatile struct CPUTIMER_REGS CpuTimer2Regs;
extern struct CPUTIMER_VARS CpuTimer2;
struct CANME_BITS {
Uint16 ME0:1;
Uint16 ME1:1;
Uint16 ME2:1;
Uint16 ME3:1;
Uint16 ME4:1;
Uint16 ME5:1;
Uint16 ME6:1;
Uint16 ME7:1;
Uint16 ME8:1;
Uint16 ME9:1;
Uint16 ME10:1;
Uint16 ME11:1;
Uint16 ME12:1;
Uint16 ME13:1;
Uint16 ME14:1;
Uint16 ME15:1;
Uint16 ME16:1;
Uint16 ME17:1;
Uint16 ME18:1;
Uint16 ME19:1;
Uint16 ME20:1;
Uint16 ME21:1;
Uint16 ME22:1;
Uint16 ME23:1;
Uint16 ME24:1;
Uint16 ME25:1;
Uint16 ME26:1;
Uint16 ME27:1;
Uint16 ME28:1;
Uint16 ME29:1;
Uint16 ME30:1;
Uint16 ME31:1;
};
union CANME_REG {
Uint32 all;
struct CANME_BITS bit;
};
struct CANMD_BITS {
Uint16 MD0:1;
Uint16 MD1:1;
Uint16 MD2:1;
Uint16 MD3:1;
Uint16 MD4:1;
Uint16 MD5:1;
Uint16 MD6:1;
Uint16 MD7:1;
Uint16 MD8:1;
Uint16 MD9:1;
Uint16 MD10:1;
Uint16 MD11:1;
Uint16 MD12:1;
Uint16 MD13:1;
Uint16 MD14:1;
Uint16 MD15:1;
Uint16 MD16:1;
Uint16 MD17:1;
Uint16 MD18:1;
Uint16 MD19:1;
Uint16 MD20:1;
Uint16 MD21:1;
Uint16 MD22:1;
Uint16 MD23:1;
Uint16 MD24:1;
Uint16 MD25:1;
Uint16 MD26:1;
Uint16 MD27:1;
Uint16 MD28:1;
Uint16 MD29:1;
Uint16 MD30:1;
Uint16 MD31:1;
};
union CANMD_REG {
Uint32 all;
struct CANMD_BITS bit;
};
struct CANTRS_BITS {
Uint16 TRS0:1;
Uint16 TRS1:1;
Uint16 TRS2:1;
Uint16 TRS3:1;
Uint16 TRS4:1;
Uint16 TRS5:1;
Uint16 TRS6:1;
Uint16 TRS7:1;
Uint16 TRS8:1;
Uint16 TRS9:1;
Uint16 TRS10:1;
Uint16 TRS11:1;
Uint16 TRS12:1;
Uint16 TRS13:1;
Uint16 TRS14:1;
Uint16 TRS15:1;
Uint16 TRS16:1;
Uint16 TRS17:1;
Uint16 TRS18:1;
Uint16 TRS19:1;
Uint16 TRS20:1;
Uint16 TRS21:1;
Uint16 TRS22:1;
Uint16 TRS23:1;
Uint16 TRS24:1;
Uint16 TRS25:1;
Uint16 TRS26:1;
Uint16 TRS27:1;
Uint16 TRS28:1;
Uint16 TRS29:1;
Uint16 TRS30:1;
Uint16 TRS31:1;
};
union CANTRS_REG {
Uint32 all;
struct CANTRS_BITS bit;
};
struct CANTRR_BITS {
Uint16 TRR0:1;
Uint16 TRR1:1;
Uint16 TRR2:1;
Uint16 TRR3:1;
Uint16 TRR4:1;
Uint16 TRR5:1;
Uint16 TRR6:1;
Uint16 TRR7:1;
Uint16 TRR8:1;
Uint16 TRR9:1;
Uint16 TRR10:1;
Uint16 TRR11:1;
Uint16 TRR12:1;
Uint16 TRR13:1;
Uint16 TRR14:1;
Uint16 TRR15:1;
Uint16 TRR16:1;
Uint16 TRR17:1;
Uint16 TRR18:1;
Uint16 TRR19:1;
Uint16 TRR20:1;
Uint16 TRR21:1;
Uint16 TRR22:1;
Uint16 TRR23:1;
Uint16 TRR24:1;
Uint16 TRR25:1;
Uint16 TRR26:1;
Uint16 TRR27:1;
Uint16 TRR28:1;
Uint16 TRR29:1;
Uint16 TRR30:1;
Uint16 TRR31:1;
};
union CANTRR_REG {
Uint32 all;
struct CANTRR_BITS bit;
};
struct CANTA_BITS {
Uint16 TA0:1;
Uint16 TA1:1;
Uint16 TA2:1;
Uint16 TA3:1;
Uint16 TA4:1;
Uint16 TA5:1;
Uint16 TA6:1;
Uint16 TA7:1;
Uint16 TA8:1;
Uint16 TA9:1;
Uint16 TA10:1;
Uint16 TA11:1;
Uint16 TA12:1;
Uint16 TA13:1;
Uint16 TA14:1;
Uint16 TA15:1;
Uint16 TA16:1;
Uint16 TA17:1;
Uint16 TA18:1;
Uint16 TA19:1;
Uint16 TA20:1;
Uint16 TA21:1;
Uint16 TA22:1;
Uint16 TA23:1;
Uint16 TA24:1;
Uint16 TA25:1;
Uint16 TA26:1;
Uint16 TA27:1;
Uint16 TA28:1;
Uint16 TA29:1;
Uint16 TA30:1;
Uint16 TA31:1;
};
union CANTA_REG {
Uint32 all;
struct CANTA_BITS bit;
};
struct CANAA_BITS {
Uint16 AA0:1;
Uint16 AA1:1;
Uint16 AA2:1;
Uint16 AA3:1;
Uint16 AA4:1;
Uint16 AA5:1;
Uint16 AA6:1;
Uint16 AA7:1;
Uint16 AA8:1;
Uint16 AA9:1;
Uint16 AA10:1;
Uint16 AA11:1;
Uint16 AA12:1;
Uint16 AA13:1;
Uint16 AA14:1;
Uint16 AA15:1;
Uint16 AA16:1;
Uint16 AA17:1;
Uint16 AA18:1;
Uint16 AA19:1;
Uint16 AA20:1;
Uint16 AA21:1;
Uint16 AA22:1;
Uint16 AA23:1;
Uint16 AA24:1;
Uint16 AA25:1;
Uint16 AA26:1;
Uint16 AA27:1;
Uint16 AA28:1;
Uint16 AA29:1;
Uint16 AA30:1;
Uint16 AA31:1;
};
union CANAA_REG {
Uint32 all;
struct CANAA_BITS bit;
};
struct CANRMP_BITS {
Uint16 RMP0:1;
Uint16 RMP1:1;
Uint16 RMP2:1;
Uint16 RMP3:1;
Uint16 RMP4:1;
Uint16 RMP5:1;
Uint16 RMP6:1;
Uint16 RMP7:1;
Uint16 RMP8:1;
Uint16 RMP9:1;
Uint16 RMP10:1;
Uint16 RMP11:1;
Uint16 RMP12:1;
Uint16 RMP13:1;
Uint16 RMP14:1;
Uint16 RMP15:1;
Uint16 RMP16:1;
Uint16 RMP17:1;
Uint16 RMP18:1;
Uint16 RMP19:1;
Uint16 RMP20:1;
Uint16 RMP21:1;
Uint16 RMP22:1;
Uint16 RMP23:1;
Uint16 RMP24:1;
Uint16 RMP25:1;
Uint16 RMP26:1;
Uint16 RMP27:1;
Uint16 RMP28:1;
Uint16 RMP29:1;
Uint16 RMP30:1;
Uint16 RMP31:1;
};
union CANRMP_REG {
Uint32 all;
struct CANRMP_BITS bit;
};
struct CANRML_BITS {
Uint16 RML0:1;
Uint16 RML1:1;
Uint16 RML2:1;
Uint16 RML3:1;
Uint16 RML4:1;
Uint16 RML5:1;
Uint16 RML6:1;
Uint16 RML7:1;
Uint16 RML8:1;
Uint16 RML9:1;
Uint16 RML10:1;
Uint16 RML11:1;
Uint16 RML12:1;
Uint16 RML13:1;
Uint16 RML14:1;
Uint16 RML15:1;
Uint16 RML16:1;
Uint16 RML17:1;
Uint16 RML18:1;
Uint16 RML19:1;
Uint16 RML20:1;
Uint16 RML21:1;
Uint16 RML22:1;
Uint16 RML23:1;
Uint16 RML24:1;
Uint16 RML25:1;
Uint16 RML26:1;
Uint16 RML27:1;
Uint16 RML28:1;
Uint16 RML29:1;
Uint16 RML30:1;
Uint16 RML31:1;
};
union CANRML_REG {
Uint32 all;
struct CANRML_BITS bit;
};
struct CANRFP_BITS {
Uint16 RFP0:1;
Uint16 RFP1:1;
Uint16 RFP2:1;
Uint16 RFP3:1;
Uint16 RFP4:1;
Uint16 RFP5:1;
Uint16 RFP6:1;
Uint16 RFP7:1;
Uint16 RFP8:1;
Uint16 RFP9:1;
Uint16 RFP10:1;
Uint16 RFP11:1;
Uint16 RFP12:1;
Uint16 RFP13:1;
Uint16 RFP14:1;
Uint16 RFP15:1;
Uint16 RFP16:1;
Uint16 RFP17:1;
Uint16 RFP18:1;
Uint16 RFP19:1;
Uint16 RFP20:1;
Uint16 RFP21:1;
Uint16 RFP22:1;
Uint16 RFP23:1;
Uint16 RFP24:1;
Uint16 RFP25:1;
Uint16 RFP26:1;
Uint16 RFP27:1;
Uint16 RFP28:1;
Uint16 RFP29:1;
Uint16 RFP30:1;
Uint16 RFP31:1;
};
union CANRFP_REG {
Uint32 all;
struct CANRFP_BITS bit;
};
struct CANGAM_BITS {
Uint16 GAM150:16;
Uint16 GAM2816:13;
Uint16 rsvd:2;
Uint16 AMI:1;
};
union CANGAM_REG {
Uint32 all;
struct CANGAM_BITS bit;
};
struct CANMC_BITS {
Uint16 MBNR:5;
Uint16 SRES:1;
Uint16 STM:1;
Uint16 ABO:1;
Uint16 CDR:1;
Uint16 WUBA:1;
Uint16 DBO:1;
Uint16 PDR:1;
Uint16 CCR:1;
Uint16 SCB:1;
Uint16 TCC:1;
Uint16 MBCC:1;
Uint16 SUSP:1;
Uint16 rsvd:15;
};
union CANMC_REG {
Uint32 all;
struct CANMC_BITS bit;
};
struct CANBTC_BITS {
Uint16 TSEG2REG:3;
Uint16 TSEG1REG:4;
Uint16 SAM:1;
Uint16 SJWREG:2;
Uint16 rsvd1:6;
Uint16 BRPREG:8;
Uint16 rsvd2:8;
};
union CANBTC_REG {
Uint32 all;
struct CANBTC_BITS bit;
};
struct CANES_BITS {
Uint16 TM:1;
Uint16 RM:1;
Uint16 rsvd1:1;
Uint16 PDA:1;
Uint16 CCE:1;
Uint16 SMA:1;
Uint16 rsvd2:10;
Uint16 EW:1;
Uint16 EP:1;
Uint16 BO:1;
Uint16 ACKE:1;
Uint16 SE:1;
Uint16 CRCE:1;
Uint16 SA1:1;
Uint16 BE:1;
Uint16 FE:1;
Uint16 rsvd3:7;
};
union CANES_REG {
Uint32 all;
struct CANES_BITS bit;
};
struct CANTEC_BITS {
Uint16 TEC:8;
Uint16 rsvd1:8;
Uint16 rsvd2:16;
};
union CANTEC_REG {
Uint32 all;
struct CANTEC_BITS bit;
};
struct CANREC_BITS {
Uint16 REC:8;
Uint16 rsvd1:8;
Uint16 rsvd2:16;
};
union CANREC_REG {
Uint32 all;
struct CANREC_BITS bit;
};
struct CANGIF0_BITS {
Uint16 MIV0:5;
Uint16 rsvd1:3;
Uint16 WLIF0:1;
Uint16 EPIF0:1;
Uint16 BOIF0:1;
Uint16 RMLIF0:1;
Uint16 WUIF0:1;
Uint16 WDIF0:1;
Uint16 AAIF0:1;
Uint16 GMIF0:1;
Uint16 TCOF0:1;
Uint16 MTOF0:1;
Uint16 rsvd2:14;
};
union CANGIF0_REG {
Uint32 all;
struct CANGIF0_BITS bit;
};
struct CANGIM_BITS {
Uint16 I0EN:1;
Uint16 I1EN:1;
Uint16 GIL:1;
Uint16 rsvd1:5;
Uint16 WLIM:1;
Uint16 EPIM:1;
Uint16 BOIM:1;
Uint16 RMLIM:1;
Uint16 WUIM:1;
Uint16 WDIM:1;
Uint16 AAIM:1;
Uint16 rsvd2:1;
Uint16 TCOM:1;
Uint16 MTOM:1;
Uint16 rsvd3:14;
};
union CANGIM_REG {
Uint32 all;
struct CANGIM_BITS bit;
};
struct CANGIF1_BITS {
Uint16 MIV1:5;
Uint16 rsvd1:3;
Uint16 WLIF1:1;
Uint16 EPIF1:1;
Uint16 BOIF1:1;
Uint16 RMLIF1:1;
Uint16 WUIF1:1;
Uint16 WDIF1:1;
Uint16 AAIF1:1;
Uint16 GMIF1:1;
Uint16 TCOF1:1;
Uint16 MTOF1:1;
Uint16 rsvd2:14;
};
union CANGIF1_REG {
Uint32 all;
struct CANGIF1_BITS bit;
};
struct CANMIM_BITS {
Uint16 MIM0:1;
Uint16 MIM1:1;
Uint16 MIM2:1;
Uint16 MIM3:1;
Uint16 MIM4:1;
Uint16 MIM5:1;
Uint16 MIM6:1;
Uint16 MIM7:1;
Uint16 MIM8:1;
Uint16 MIM9:1;
Uint16 MIM10:1;
Uint16 MIM11:1;
Uint16 MIM12:1;
Uint16 MIM13:1;
Uint16 MIM14:1;
Uint16 MIM15:1;
Uint16 MIM16:1;
Uint16 MIM17:1;
Uint16 MIM18:1;
Uint16 MIM19:1;
Uint16 MIM20:1;
Uint16 MIM21:1;
Uint16 MIM22:1;
Uint16 MIM23:1;
Uint16 MIM24:1;
Uint16 MIM25:1;
Uint16 MIM26:1;
Uint16 MIM27:1;
Uint16 MIM28:1;
Uint16 MIM29:1;
Uint16 MIM30:1;
Uint16 MIM31:1;
};
union CANMIM_REG {
Uint32 all;
struct CANMIM_BITS bit;
};
struct CANMIL_BITS {
Uint16 MIL0:1;
Uint16 MIL1:1;
Uint16 MIL2:1;
Uint16 MIL3:1;
Uint16 MIL4:1;
Uint16 MIL5:1;
Uint16 MIL6:1;
Uint16 MIL7:1;
Uint16 MIL8:1;
Uint16 MIL9:1;
Uint16 MIL10:1;
Uint16 MIL11:1;
Uint16 MIL12:1;
Uint16 MIL13:1;
Uint16 MIL14:1;
Uint16 MIL15:1;
Uint16 MIL16:1;
Uint16 MIL17:1;
Uint16 MIL18:1;
Uint16 MIL19:1;
Uint16 MIL20:1;
Uint16 MIL21:1;
Uint16 MIL22:1;
Uint16 MIL23:1;
Uint16 MIL24:1;
Uint16 MIL25:1;
Uint16 MIL26:1;
Uint16 MIL27:1;
Uint16 MIL28:1;
Uint16 MIL29:1;
Uint16 MIL30:1;
Uint16 MIL31:1;
};
union CANMIL_REG {
Uint32 all;
struct CANMIL_BITS bit;
};
struct CANOPC_BITS {
Uint16 OPC0:1;
Uint16 OPC1:1;
Uint16 OPC2:1;
Uint16 OPC3:1;
Uint16 OPC4:1;
Uint16 OPC5:1;
Uint16 OPC6:1;
Uint16 OPC7:1;
Uint16 OPC8:1;
Uint16 OPC9:1;
Uint16 OPC10:1;
Uint16 OPC11:1;
Uint16 OPC12:1;
Uint16 OPC13:1;
Uint16 OPC14:1;
Uint16 OPC15:1;
Uint16 OPC16:1;
Uint16 OPC17:1;
Uint16 OPC18:1;
Uint16 OPC19:1;
Uint16 OPC20:1;
Uint16 OPC21:1;
Uint16 OPC22:1;
Uint16 OPC23:1;
Uint16 OPC24:1;
Uint16 OPC25:1;
Uint16 OPC26:1;
Uint16 OPC27:1;
Uint16 OPC28:1;
Uint16 OPC29:1;
Uint16 OPC30:1;
Uint16 OPC31:1;
};
union CANOPC_REG {
Uint32 all;
struct CANOPC_BITS bit;
};
struct CANTIOC_BITS {
Uint16 rsvd1:3;
Uint16 TXFUNC:1;
Uint16 rsvd2:12;
Uint16 rsvd3:16;
};
union CANTIOC_REG {
Uint32 all;
struct CANTIOC_BITS bit;
};
struct CANRIOC_BITS {
Uint16 rsvd1:3;
Uint16 RXFUNC:1;
Uint16 rsvd2:12;
Uint16 rsvd3:16;
};
union CANRIOC_REG {
Uint32 all;
struct CANRIOC_BITS bit;
};
struct CANTOC_BITS {
Uint16 TOC0:1;
Uint16 TOC1:1;
Uint16 TOC2:1;
Uint16 TOC3:1;
Uint16 TOC4:1;
Uint16 TOC5:1;
Uint16 TOC6:1;
Uint16 TOC7:1;
Uint16 TOC8:1;
Uint16 TOC9:1;
Uint16 TOC10:1;
Uint16 TOC11:1;
Uint16 TOC12:1;
Uint16 TOC13:1;
Uint16 TOC14:1;
Uint16 TOC15:1;
Uint16 TOC16:1;
Uint16 TOC17:1;
Uint16 TOC18:1;
Uint16 TOC19:1;
Uint16 TOC20:1;
Uint16 TOC21:1;
Uint16 TOC22:1;
Uint16 TOC23:1;
Uint16 TOC24:1;
Uint16 TOC25:1;
Uint16 TOC26:1;
Uint16 TOC27:1;
Uint16 TOC28:1;
Uint16 TOC29:1;
Uint16 TOC30:1;
Uint16 TOC31:1;
};
union CANTOC_REG {
Uint32 all;
struct CANTOC_BITS bit;
};
struct CANTOS_BITS {
Uint16 TOS0:1;
Uint16 TOS1:1;
Uint16 TOS2:1;
Uint16 TOS3:1;
Uint16 TOS4:1;
Uint16 TOS5:1;
Uint16 TOS6:1;
Uint16 TOS7:1;
Uint16 TOS8:1;
Uint16 TOS9:1;
Uint16 TOS10:1;
Uint16 TOS11:1;
Uint16 TOS12:1;
Uint16 TOS13:1;
Uint16 TOS14:1;
Uint16 TOS15:1;
Uint16 TOS16:1;
Uint16 TOS17:1;
Uint16 TOS18:1;
Uint16 TOS19:1;
Uint16 TOS20:1;
Uint16 TOS21:1;
Uint16 TOS22:1;
Uint16 TOS23:1;
Uint16 TOS24:1;
Uint16 TOS25:1;
Uint16 TOS26:1;
Uint16 TOS27:1;
Uint16 TOS28:1;
Uint16 TOS29:1;
Uint16 TOS30:1;
Uint16 TOS31:1;
};
union CANTOS_REG {
Uint32 all;
struct CANTOS_BITS bit;
};
struct ECAN_REGS {
union CANME_REG CANME;
union CANMD_REG CANMD;
union CANTRS_REG CANTRS;
union CANTRR_REG CANTRR;
union CANTA_REG CANTA;
union CANAA_REG CANAA;
union CANRMP_REG CANRMP;
union CANRML_REG CANRML;
union CANRFP_REG CANRFP;
union CANGAM_REG CANGAM;
union CANMC_REG CANMC;
union CANBTC_REG CANBTC;
union CANES_REG CANES;
union CANTEC_REG CANTEC;
union CANREC_REG CANREC;
union CANGIF0_REG CANGIF0;
union CANGIM_REG CANGIM;
union CANGIF1_REG CANGIF1;
union CANMIM_REG CANMIM;
union CANMIL_REG CANMIL;
union CANOPC_REG CANOPC;
union CANTIOC_REG CANTIOC;
union CANRIOC_REG CANRIOC;
Uint32 CANTSC;
union CANTOC_REG CANTOC;
union CANTOS_REG CANTOS;
};
struct CANMSGID_BITS {
Uint16 EXTMSGID_L:16;
Uint16 EXTMSGID_H:2;
Uint16 STDMSGID:11;
Uint16 AAM:1;
Uint16 AME:1;
Uint16 IDE:1;
};
union CANMSGID_REG {
Uint32 all;
struct CANMSGID_BITS bit;
};
struct CANMSGCTRL_BITS {
Uint16 DLC:4;
Uint16 RTR:1;
Uint16 rsvd1:3;
Uint16 TPL:5;
Uint16 rsvd2:3;
Uint16 rsvd3:16;
};
union CANMSGCTRL_REG {
Uint32 all;
struct CANMSGCTRL_BITS bit;
};
struct CANMDL_WORDS {
Uint16 LOW_WORD:16;
Uint16 HI_WORD:16;
};
struct CANMDL_BYTES {
Uint16 BYTE3:8;
Uint16 BYTE2:8;
Uint16 BYTE1:8;
Uint16 BYTE0:8;
};
union CANMDL_REG {
Uint32 all;
struct CANMDL_WORDS word;
struct CANMDL_BYTES byte;
};
struct CANMDH_WORDS {
Uint16 LOW_WORD:16;
Uint16 HI_WORD:16;
};
struct CANMDH_BYTES {
Uint16 BYTE7:8;
Uint16 BYTE6:8;
Uint16 BYTE5:8;
Uint16 BYTE4:8;
};
union CANMDH_REG {
Uint32 all;
struct CANMDH_WORDS word;
struct CANMDH_BYTES byte;
};
struct MBOX {
union CANMSGID_REG MSGID;
union CANMSGCTRL_REG MSGCTRL;
union CANMDL_REG MDL;
union CANMDH_REG MDH;
};
struct ECAN_MBOXES {
struct MBOX MBOX0;
struct MBOX MBOX1;
struct MBOX MBOX2;
struct MBOX MBOX3;
struct MBOX MBOX4;
struct MBOX MBOX5;
struct MBOX MBOX6;
struct MBOX MBOX7;
struct MBOX MBOX8;
struct MBOX MBOX9;
struct MBOX MBOX10;
struct MBOX MBOX11;
struct MBOX MBOX12;
struct MBOX MBOX13;
struct MBOX MBOX14;
struct MBOX MBOX15;
struct MBOX MBOX16;
struct MBOX MBOX17;
struct MBOX MBOX18;
struct MBOX MBOX19;
struct MBOX MBOX20;
struct MBOX MBOX21;
struct MBOX MBOX22;
struct MBOX MBOX23;
struct MBOX MBOX24;
struct MBOX MBOX25;
struct MBOX MBOX26;
struct MBOX MBOX27;
struct MBOX MBOX28;
struct MBOX MBOX29;
struct MBOX MBOX30;
struct MBOX MBOX31;
};
struct CANLAM_BITS {
Uint16 LAM_L:16;
Uint16 LAM_H:13;
Uint16 rsvd1:2;
Uint16 LAMI:1;
};
union CANLAM_REG {
Uint32 all;
struct CANLAM_BITS bit;
};
struct LAM_REGS {
union CANLAM_REG LAM0;
union CANLAM_REG LAM1;
union CANLAM_REG LAM2;
union CANLAM_REG LAM3;
union CANLAM_REG LAM4;
union CANLAM_REG LAM5;
union CANLAM_REG LAM6;
union CANLAM_REG LAM7;
union CANLAM_REG LAM8;
union CANLAM_REG LAM9;
union CANLAM_REG LAM10;
union CANLAM_REG LAM11;
union CANLAM_REG LAM12;
union CANLAM_REG LAM13;
union CANLAM_REG LAM14;
union CANLAM_REG LAM15;
union CANLAM_REG LAM16;
union CANLAM_REG LAM17;
union CANLAM_REG LAM18;
union CANLAM_REG LAM19;
union CANLAM_REG LAM20;
union CANLAM_REG LAM21;
union CANLAM_REG LAM22;
union CANLAM_REG LAM23;
union CANLAM_REG LAM24;
union CANLAM_REG LAM25;
union CANLAM_REG LAM26;
union CANLAM_REG LAM27;
union CANLAM_REG LAM28;
union CANLAM_REG LAM29;
union CANLAM_REG LAM30;
union CANLAM_REG LAM31;
};
struct MOTS_REGS {
Uint32 MOTS0;
Uint32 MOTS1;
Uint32 MOTS2;
Uint32 MOTS3;
Uint32 MOTS4;
Uint32 MOTS5;
Uint32 MOTS6;
Uint32 MOTS7;
Uint32 MOTS8;
Uint32 MOTS9;
Uint32 MOTS10;
Uint32 MOTS11;
Uint32 MOTS12;
Uint32 MOTS13;
Uint32 MOTS14;
Uint32 MOTS15;
Uint32 MOTS16;
Uint32 MOTS17;
Uint32 MOTS18;
Uint32 MOTS19;
Uint32 MOTS20;
Uint32 MOTS21;
Uint32 MOTS22;
Uint32 MOTS23;
Uint32 MOTS24;
Uint32 MOTS25;
Uint32 MOTS26;
Uint32 MOTS27;
Uint32 MOTS28;
Uint32 MOTS29;
Uint32 MOTS30;
Uint32 MOTS31;
};
struct MOTO_REGS {
Uint32 MOTO0;
Uint32 MOTO1;
Uint32 MOTO2;
Uint32 MOTO3;
Uint32 MOTO4;
Uint32 MOTO5;
Uint32 MOTO6;
Uint32 MOTO7;
Uint32 MOTO8;
Uint32 MOTO9;
Uint32 MOTO10;
Uint32 MOTO11;
Uint32 MOTO12;
Uint32 MOTO13;
Uint32 MOTO14;
Uint32 MOTO15;
Uint32 MOTO16;
Uint32 MOTO17;
Uint32 MOTO18;
Uint32 MOTO19;
Uint32 MOTO20;
Uint32 MOTO21;
Uint32 MOTO22;
Uint32 MOTO23;
Uint32 MOTO24;
Uint32 MOTO25;
Uint32 MOTO26;
Uint32 MOTO27;
Uint32 MOTO28;
Uint32 MOTO29;
Uint32 MOTO30;
Uint32 MOTO31;
};
extern volatile struct ECAN_REGS ECanaRegs;
extern volatile struct ECAN_MBOXES ECanaMboxes;
extern volatile struct LAM_REGS ECanaLAMRegs;
extern volatile struct MOTO_REGS ECanaMOTORegs;
extern volatile struct MOTS_REGS ECanaMOTSRegs;
extern volatile struct ECAN_REGS ECanbRegs;
extern volatile struct ECAN_MBOXES ECanbMboxes;
extern volatile struct LAM_REGS ECanbLAMRegs;
extern volatile struct MOTO_REGS ECanbMOTORegs;
extern volatile struct MOTS_REGS ECanbMOTSRegs;
struct ECCTL1_BITS {
Uint16 CAP1POL:1;
Uint16 CTRRST1:1;
Uint16 CAP2POL:1;
Uint16 CTRRST2:1;
Uint16 CAP3POL:1;
Uint16 CTRRST3:1;
Uint16 CAP4POL:1;
Uint16 CTRRST4:1;
Uint16 CAPLDEN:1;
Uint16 PRESCALE:5;
Uint16 FREE_SOFT:2;
};
union ECCTL1_REG {
Uint16 all;
struct ECCTL1_BITS bit;
};
struct ECCTL2_BITS {
Uint16 CONT_ONESHT:1;
Uint16 STOP_WRAP:2;
Uint16 REARM:1;
Uint16 TSCTRSTOP:1;
Uint16 SYNCI_EN:1;
Uint16 SYNCO_SEL:2;
Uint16 SWSYNC:1;
Uint16 CAP_APWM:1;
Uint16 APWMPOL:1;
Uint16 rsvd1:5;
};
union ECCTL2_REG {
Uint16 all;
struct ECCTL2_BITS bit;
};
struct ECEINT_BITS {
Uint16 rsvd1:1;
Uint16 CEVT1:1;
Uint16 CEVT2:1;
Uint16 CEVT3:1;
Uint16 CEVT4:1;
Uint16 CTROVF:1;
Uint16 CTR_EQ_PRD:1;
Uint16 CTR_EQ_CMP:1;
Uint16 rsvd2:8;
};
union ECEINT_REG {
Uint16 all;
struct ECEINT_BITS bit;
};
struct ECFLG_BITS {
Uint16 INT:1;
Uint16 CEVT1:1;
Uint16 CEVT2:1;
Uint16 CEVT3:1;
Uint16 CEVT4:1;
Uint16 CTROVF:1;
Uint16 CTR_EQ_PRD:1;
Uint16 CTR_EQ_CMP:1;
Uint16 rsvd2:8;
};
union ECFLG_REG {
Uint16 all;
struct ECFLG_BITS bit;
};
struct ECAP_REGS {
Uint32 TSCTR;
Uint32 CTRPHS;
Uint32 CAP1;
Uint32 CAP2;
Uint32 CAP3;
Uint32 CAP4;
Uint16 rsvd1[8];
union ECCTL1_REG ECCTL1;
union ECCTL2_REG ECCTL2;
union ECEINT_REG ECEINT;
union ECFLG_REG ECFLG;
union ECFLG_REG ECCLR;
union ECEINT_REG ECFRC;
Uint16 rsvd2[6];
};
extern volatile struct ECAP_REGS ECap1Regs;
extern volatile struct ECAP_REGS ECap2Regs;
extern volatile struct ECAP_REGS ECap3Regs;
extern volatile struct ECAP_REGS ECap4Regs;
struct TBCTL_BITS {
Uint16 CTRMODE:2;
Uint16 PHSEN:1;
Uint16 PRDLD:1;
Uint16 SYNCOSEL:2;
Uint16 SWFSYNC:1;
Uint16 HSPCLKDIV:3;
Uint16 CLKDIV:3;
Uint16 PHSDIR:1;
Uint16 FREE_SOFT:2;
};
union TBCTL_REG {
Uint16 all;
struct TBCTL_BITS bit;
};
struct TBSTS_BITS {
Uint16 CTRDIR:1;
Uint16 SYNCI:1;
Uint16 CTRMAX:1;
Uint16 rsvd1:13;
};
union TBSTS_REG {
Uint16 all;
struct TBSTS_BITS bit;
};
struct CMPCTL_BITS {
Uint16 LOADAMODE:2;
Uint16 LOADBMODE:2;
Uint16 SHDWAMODE:1;
Uint16 rsvd1:1;
Uint16 SHDWBMODE:1;
Uint16 rsvd2:1;
Uint16 SHDWAFULL:1;
Uint16 SHDWBFULL:1;
Uint16 rsvd3:6;
};
union CMPCTL_REG {
Uint16 all;
struct CMPCTL_BITS bit;
};
struct AQCTL_BITS {
Uint16 ZRO:2;
Uint16 PRD:2;
Uint16 CAU:2;
Uint16 CAD:2;
Uint16 CBU:2;
Uint16 CBD:2;
Uint16 rsvd:4;
};
union AQCTL_REG {
Uint16 all;
struct AQCTL_BITS bit;
};
struct AQSFRC_BITS {
Uint16 ACTSFA:2;
Uint16 OTSFA:1;
Uint16 ACTSFB:2;
Uint16 OTSFB:1;
Uint16 RLDCSF:2;
Uint16 rsvd1:8;
};
union AQSFRC_REG {
Uint16 all;
struct AQSFRC_BITS bit;
};
struct AQCSFRC_BITS {
Uint16 CSFA:2;
Uint16 CSFB:2;
Uint16 rsvd1:12;
};
union AQCSFRC_REG {
Uint16 all;
struct AQCSFRC_BITS bit;
};
struct DBCTL_BITS {
Uint16 OUT_MODE:2;
Uint16 POLSEL:2;
Uint16 IN_MODE:2;
Uint16 rsvd1:10;
};
union DBCTL_REG {
Uint16 all;
struct DBCTL_BITS bit;
};
struct TZSEL_BITS {
Uint16 CBC1:1;
Uint16 CBC2:1;
Uint16 CBC3:1;
Uint16 CBC4:1;
Uint16 CBC5:1;
Uint16 CBC6:1;
Uint16 rsvd1:2;
Uint16 OSHT1:1;
Uint16 OSHT2:1;
Uint16 OSHT3:1;
Uint16 OSHT4:1;
Uint16 OSHT5:1;
Uint16 OSHT6:1;
Uint16 rsvd2:2;
};
union TZSEL_REG {
Uint16 all;
struct TZSEL_BITS bit;
};
struct TZCTL_BITS {
Uint16 TZA:2;
Uint16 TZB:2;
Uint16 rsvd:12;
};
union TZCTL_REG {
Uint16 all;
struct TZCTL_BITS bit;
};
struct TZEINT_BITS {
Uint16 rsvd1:1;
Uint16 CBC:1;
Uint16 OST:1;
Uint16 rsvd2:13;
};
union TZEINT_REG {
Uint16 all;
struct TZEINT_BITS bit;
};
struct TZFLG_BITS {
Uint16 INT:1;
Uint16 CBC:1;
Uint16 OST:1;
Uint16 rsvd2:13;
};
union TZFLG_REG {
Uint16 all;
struct TZFLG_BITS bit;
};
struct TZCLR_BITS {
Uint16 INT:1;
Uint16 CBC:1;
Uint16 OST:1;
Uint16 rsvd2:13;
};
union TZCLR_REG {
Uint16 all;
struct TZCLR_BITS bit;
};
struct TZFRC_BITS {
Uint16 rsvd1:1;
Uint16 CBC:1;
Uint16 OST:1;
Uint16 rsvd2:13;
};
union TZFRC_REG {
Uint16 all;
struct TZFRC_BITS bit;
};
struct ETSEL_BITS {
Uint16 INTSEL:3;
Uint16 INTEN:1;
Uint16 rsvd1:4;
Uint16 SOCASEL:3;
Uint16 SOCAEN:1;
Uint16 SOCBSEL:3;
Uint16 SOCBEN:1;
};
union ETSEL_REG {
Uint16 all;
struct ETSEL_BITS bit;
};
struct ETPS_BITS {
Uint16 INTPRD:2;
Uint16 INTCNT:2;
Uint16 rsvd1:4;
Uint16 SOCAPRD:2;
Uint16 SOCACNT:2;
Uint16 SOCBPRD:2;
Uint16 SOCBCNT:2;
};
union ETPS_REG {
Uint16 all;
struct ETPS_BITS bit;
};
struct ETFLG_BITS {
Uint16 INT:1;
Uint16 rsvd1:1;
Uint16 SOCA:1;
Uint16 SOCB:1;
Uint16 rsvd2:12;
};
union ETFLG_REG {
Uint16 all;
struct ETFLG_BITS bit;
};
struct ETCLR_BITS {
Uint16 INT:1;
Uint16 rsvd1:1;
Uint16 SOCA:1;
Uint16 SOCB:1;
Uint16 rsvd2:12;
};
union ETCLR_REG {
Uint16 all;
struct ETCLR_BITS bit;
};
struct ETFRC_BITS {
Uint16 INT:1;
Uint16 rsvd1:1;
Uint16 SOCA:1;
Uint16 SOCB:1;
Uint16 rsvd2:12;
};
union ETFRC_REG {
Uint16 all;
struct ETFRC_BITS bit;
};
struct PCCTL_BITS {
Uint16 CHPEN:1;
Uint16 OSHTWTH:4;
Uint16 CHPFREQ:3;
Uint16 CHPDUTY:3;
Uint16 rsvd1:5;
};
union PCCTL_REG {
Uint16 all;
struct PCCTL_BITS bit;
};
struct HRCNFG_BITS {
Uint16 EDGMODE:2;
Uint16 CTLMODE:1;
Uint16 HRLOAD:1;
Uint16 rsvd1:12;
};
union HRCNFG_REG {
Uint16 all;
struct HRCNFG_BITS bit;
};
struct TBPHS_HRPWM_REG {
Uint16 TBPHSHR;
Uint16 TBPHS;
};
union TBPHS_HRPWM_GROUP {
Uint32 all;
struct TBPHS_HRPWM_REG half;
};
struct CMPA_HRPWM_REG {
Uint16 CMPAHR;
Uint16 CMPA;
};
union CMPA_HRPWM_GROUP {
Uint32 all;
struct CMPA_HRPWM_REG half;
};
struct EPWM_REGS {
union TBCTL_REG TBCTL;
union TBSTS_REG TBSTS;
union TBPHS_HRPWM_GROUP TBPHS;
Uint16 TBCTR;
Uint16 TBPRD;
Uint16 rsvd1;
union CMPCTL_REG CMPCTL;
union CMPA_HRPWM_GROUP CMPA;
Uint16 CMPB;
union AQCTL_REG AQCTLA;
union AQCTL_REG AQCTLB;
union AQSFRC_REG AQSFRC;
union AQCSFRC_REG AQCSFRC;
union DBCTL_REG DBCTL;
Uint16 DBRED;
Uint16 DBFED;
union TZSEL_REG TZSEL;
Uint16 rsvd2;
union TZCTL_REG TZCTL;
union TZEINT_REG TZEINT;
union TZFLG_REG TZFLG;
union TZCLR_REG TZCLR;
union TZFRC_REG TZFRC;
union ETSEL_REG ETSEL;
union ETPS_REG ETPS;
union ETFLG_REG ETFLG;
union ETCLR_REG ETCLR;
union ETFRC_REG ETFRC;
union PCCTL_REG PCCTL;
Uint16 rsvd3;
union HRCNFG_REG HRCNFG;
};
extern volatile struct EPWM_REGS EPwm1Regs;
extern volatile struct EPWM_REGS EPwm2Regs;
extern volatile struct EPWM_REGS EPwm3Regs;
extern volatile struct EPWM_REGS EPwm4Regs;
extern volatile struct EPWM_REGS EPwm5Regs;
extern volatile struct EPWM_REGS EPwm6Regs;
struct QDECCTL_BITS {
Uint16 rsvd1:5;
Uint16 QSP:1;
Uint16 QIP:1;
Uint16 QBP:1;
Uint16 QAP:1;
Uint16 IGATE:1;
Uint16 SWAP:1;
Uint16 XCR:1;
Uint16 SPSEL:1;
Uint16 SOEN:1;
Uint16 QSRC:2;
};
union QDECCTL_REG {
Uint16 all;
struct QDECCTL_BITS bit;
};
struct QEPCTL_BITS {
Uint16 WDE:1;
Uint16 UTE:1;
Uint16 QCLM:1;
Uint16 QPEN:1;
Uint16 IEL:2;
Uint16 SEL:1;
Uint16 SWI:1;
Uint16 IEI:2;
Uint16 SEI:2;
Uint16 PCRM:2;
Uint16 FREE_SOFT:2;
};
union QEPCTL_REG {
Uint16 all;
struct QEPCTL_BITS bit;
};
struct QCAPCTL_BITS {
Uint16 UPPS:4;
Uint16 CCPS:3;
Uint16 rsvd1:8;
Uint16 CEN:1;
};
union QCAPCTL_REG {
Uint16 all;
struct QCAPCTL_BITS bit;
};
struct QPOSCTL_BITS {
Uint16 PCSPW:12;
Uint16 PCE:1;
Uint16 PCPOL:1;
Uint16 PCLOAD:1;
Uint16 PCSHDW:1;
};
union QPOSCTL_REG {
Uint16 all;
struct QPOSCTL_BITS bit;
};
struct QEINT_BITS {
Uint16 rsvd1:1;
Uint16 PCE:1;
Uint16 QPE:1;
Uint16 QDC:1;
Uint16 WTO:1;
Uint16 PCU:1;
Uint16 PCO:1;
Uint16 PCR:1;
Uint16 PCM:1;
Uint16 SEL:1;
Uint16 IEL:1;
Uint16 UTO:1;
Uint16 rsvd2:4;
};
union QEINT_REG {
Uint16 all;
struct QEINT_BITS bit;
};
struct QFLG_BITS {
Uint16 INT:1;
Uint16 PCE:1;
Uint16 PHE:1;
Uint16 QDC:1;
Uint16 WTO:1;
Uint16 PCU:1;
Uint16 PCO:1;
Uint16 PCR:1;
Uint16 PCM:1;
Uint16 SEL:1;
Uint16 IEL:1;
Uint16 UTO:1;
Uint16 rsvd2:4;
};
union QFLG_REG {
Uint16 all;
struct QFLG_BITS bit;
};
struct QFRC_BITS {
Uint16 reserved:1;
Uint16 PCE:1;
Uint16 PHE:1;
Uint16 QDC:1;
Uint16 WTO:1;
Uint16 PCU:1;
Uint16 PCO:1;
Uint16 PCR:1;
Uint16 PCM:1;
Uint16 SEL:1;
Uint16 IEL:1;
Uint16 UTO:1;
Uint16 rsvd2:4;
};
union QFRC_REG {
Uint16 all;
struct QFRC_BITS bit;
};
struct QEPSTS_BITS {
Uint16 PCEF:1;
Uint16 FIMF:1;
Uint16 CDEF:1;
Uint16 COEF:1;
Uint16 QDLF:1;
Uint16 QDF:1;
Uint16 FIDF:1;
Uint16 UPEVNT:1;
Uint16 rsvd1:8;
};
union QEPSTS_REG {
Uint16 all;
struct QEPSTS_BITS bit;
};
struct EQEP_REGS {
Uint32 QPOSCNT;
Uint32 QPOSINIT;
Uint32 QPOSMAX;
Uint32 QPOSCMP;
Uint32 QPOSILAT;
Uint32 QPOSSLAT;
Uint32 QPOSLAT;
Uint32 QUTMR;
Uint32 QUPRD;
Uint16 QWDTMR;
Uint16 QWDPRD;
union QDECCTL_REG QDECCTL;
union QEPCTL_REG QEPCTL;
union QCAPCTL_REG QCAPCTL;
union QPOSCTL_REG QPOSCTL;
union QEINT_REG QEINT;
union QFLG_REG QFLG;
union QFLG_REG QCLR;
union QFRC_REG QFRC;
union QEPSTS_REG QEPSTS;
Uint16 QCTMR;
Uint16 QCPRD;
Uint16 QCTMRLAT;
Uint16 QCPRDLAT;
Uint16 rsvd1[30];
};
extern volatile struct EQEP_REGS EQep1Regs;
extern volatile struct EQEP_REGS EQep2Regs;
struct GPACTRL_BITS {
Uint16 QUALPRD0:8;
Uint16 QUALPRD1:8;
Uint16 QUALPRD2:8;
Uint16 QUALPRD3:8;
};
union GPACTRL_REG {
Uint32 all;
struct GPACTRL_BITS bit;
};
struct GPBCTRL_BITS {
Uint16 QUALPRD0:8;
Uint16 rsvd1:8;
Uint16 rsvd2:16;
};
union GPBCTRL_REG {
Uint32 all;
struct GPBCTRL_BITS bit;
};
struct GPA1_BITS {
Uint16 GPIO0:2;
Uint16 GPIO1:2;
Uint16 GPIO2:2;
Uint16 GPIO3:2;
Uint16 GPIO4:2;
Uint16 GPIO5:2;
Uint16 GPIO6:2;
Uint16 GPIO7:2;
Uint16 GPIO8:2;
Uint16 GPIO9:2;
Uint16 GPIO10:2;
Uint16 GPIO11:2;
Uint16 GPIO12:2;
Uint16 GPIO13:2;
Uint16 GPIO14:2;
Uint16 GPIO15:2;
};
struct GPA2_BITS {
Uint16 GPIO16:2;
Uint16 GPIO17:2;
Uint16 GPIO18:2;
Uint16 GPIO19:2;
Uint16 GPIO20:2;
Uint16 GPIO21:2;
Uint16 GPIO22:2;
Uint16 GPIO23:2;
Uint16 GPIO24:2;
Uint16 GPIO25:2;
Uint16 GPIO26:2;
Uint16 GPIO27:2;
Uint16 GPIO28:2;
Uint16 GPIO29:2;
Uint16 GPIO30:2;
Uint16 GPIO31:2;
};
struct GPB1_BITS {
Uint16 GPIO32:2;
Uint16 GPIO33:2;
Uint16 GPIO34:2;
Uint16 rsvd1:2;
Uint16 rsvd2:8;
Uint16 rsvd3:16;
};
struct GPB2_BITS {
Uint16 rsvd1:16;
Uint16 rsvd2:16;
};
union GPA1_REG {
Uint32 all;
struct GPA1_BITS bit;
};
union GPA2_REG {
Uint32 all;
struct GPA2_BITS bit;
};
union GPB1_REG {
Uint32 all;
struct GPB1_BITS bit;
};
union GPB2_REG {
Uint32 all;
struct GPB2_BITS bit;
};
struct GPADAT_BITS {
Uint16 GPIO0:1;
Uint16 GPIO1:1;
Uint16 GPIO2:1;
Uint16 GPIO3:1;
Uint16 GPIO4:1;
Uint16 GPIO5:1;
Uint16 GPIO6:1;
Uint16 GPIO7:1;
Uint16 GPIO8:1;
Uint16 GPIO9:1;
Uint16 GPIO10:1;
Uint16 GPIO11:1;
Uint16 GPIO12:1;
Uint16 GPIO13:1;
Uint16 GPIO14:1;
Uint16 GPIO15:1;
Uint16 GPIO16:1;
Uint16 GPIO17:1;
Uint16 GPIO18:1;
Uint16 GPIO19:1;
Uint16 GPIO20:1;
Uint16 GPIO21:1;
Uint16 GPIO22:1;
Uint16 GPIO23:1;
Uint16 GPIO24:1;
Uint16 GPIO25:1;
Uint16 GPIO26:1;
Uint16 GPIO27:1;
Uint16 GPIO28:1;
Uint16 GPIO29:1;
Uint16 GPIO30:1;
Uint16 GPIO31:1;
};
struct GPBDAT_BITS {
Uint16 GPIO32:1;
Uint16 GPIO33:1;
Uint16 GPIO34:1;
Uint16 rsvd1:13;
Uint16 rsvd2:16;
};
union GPADAT_REG {
Uint32 all;
struct GPADAT_BITS bit;
};
union GPBDAT_REG {
Uint32 all;
struct GPBDAT_BITS bit;
};
struct GPBPUD_BITS {
Uint16 GPIO32:1;
Uint16 GPIO33:1;
Uint16 GPIO34:1;
Uint16 GPIO35:1;
Uint16 rsvd1:12;
Uint16 rsvd2:16;
};
union GPBPUD_REG {
Uint32 all;
struct GPBPUD_BITS bit;
};
struct GPIOXINT_BITS {
Uint16 GPIOSEL:5;
Uint16 rsvd1:11;
};
union GPIOXINT_REG {
Uint16 all;
struct GPIOXINT_BITS bit;
};
struct GPIO_CTRL_REGS {
union GPACTRL_REG GPACTRL;
union GPA1_REG GPAQSEL1;
union GPA2_REG GPAQSEL2;
union GPA1_REG GPAMUX1;
union GPA2_REG GPAMUX2;
union GPADAT_REG GPADIR;
union GPADAT_REG GPAPUD;
Uint32 rsvd1;
union GPBCTRL_REG GPBCTRL;
union GPB1_REG GPBQSEL1;
union GPB2_REG GPBQSEL2;
union GPB1_REG GPBMUX1;
union GPB2_REG GPBMUX2;
union GPBDAT_REG GPBDIR;
union GPBPUD_REG GPBPUD;
Uint16 rsvd2[33];
};
struct GPIO_DATA_REGS {
union GPADAT_REG GPADAT;
union GPADAT_REG GPASET;
union GPADAT_REG GPACLEAR;
union GPADAT_REG GPATOGGLE;
union GPBPUD_REG GPBDAT;
union GPBDAT_REG GPBSET;
union GPBDAT_REG GPBCLEAR;
union GPBDAT_REG GPBTOGGLE;
Uint16 rsvd1[16];
};
struct GPIO_INT_REGS {
union GPIOXINT_REG GPIOXINT1SEL;
union GPIOXINT_REG GPIOXINT2SEL;
union GPIOXINT_REG GPIOXNMISEL;
Uint16 rsvd2[5];
union GPADAT_REG GPIOLPMSEL;
};
extern volatile struct GPIO_CTRL_REGS GpioCtrlRegs;
extern volatile struct GPIO_DATA_REGS GpioDataRegs;
extern volatile struct GPIO_INT_REGS GpioIntRegs;
struct I2CISRC_BITS {
Uint16 INTCODE:3;
Uint16 rsvd1:13;
};
union I2CISRC_REG {
Uint16 all;
struct I2CISRC_BITS bit;
};
struct I2CIER_BITS {
Uint16 AL:1;
Uint16 NACK:1;
Uint16 ARDY:1;
Uint16 RRDY:1;
Uint16 XRDY:1;
Uint16 SCD:1;
Uint16 AAS:1;
Uint16 rsvd:9;
};
union I2CIER_REG {
Uint16 all;
struct I2CIER_BITS bit;
};
struct I2CSTR_BITS {
Uint16 AL:1;
Uint16 NACK:1;
Uint16 ARDY:1;
Uint16 RRDY:1;
Uint16 XRDY:1;
Uint16 SCD:1;
Uint16 rsvd1:2;
Uint16 AD0:1;
Uint16 AAS:1;
Uint16 XSMT:1;
Uint16 RSFULL:1;
Uint16 BB:1;
Uint16 NACKSNT:1;
Uint16 SDIR:1;
Uint16 rsvd2:1;
};
union I2CSTR_REG {
Uint16 all;
struct I2CSTR_BITS bit;
};
struct I2CMDR_BITS {
Uint16 BC:3;
Uint16 FDF:1;
Uint16 STB:1;
Uint16 IRS:1;
Uint16 DLB:1;
Uint16 RM:1;
Uint16 XA:1;
Uint16 TRX:1;
Uint16 MST:1;
Uint16 STP:1;
Uint16 rsvd1:1;
Uint16 STT:1;
Uint16 FREE:1;
Uint16 NACKMOD:1;
};
union I2CMDR_REG {
Uint16 all;
struct I2CMDR_BITS bit;
};
struct I2CPSC_BITS {
Uint16 IPSC:8;
Uint16 rsvd1:8;
};
union I2CPSC_REG {
Uint16 all;
struct I2CPSC_BITS bit;
};
struct I2CFFTX_BITS {
Uint16 TXFFIL:5;
Uint16 TXFFIENA:1;
Uint16 TXFFINTCLR:1;
Uint16 TXFFINT:1;
Uint16 TXFFST:5;
Uint16 TXFFRST:1;
Uint16 I2CFFEN:1;
Uint16 rsvd1:1;
};
union I2CFFTX_REG {
Uint16 all;
struct I2CFFTX_BITS bit;
};
struct I2CFFRX_BITS {
Uint16 RXFFIL:5;
Uint16 RXFFIENA:1;
Uint16 RXFFINTCLR:1;
Uint16 RXFFINT:1;
Uint16 RXFFST:5;
Uint16 RXFFRST:1;
Uint16 rsvd1:2;
};
union I2CFFRX_REG {
Uint16 all;
struct I2CFFRX_BITS bit;
};
struct I2C_REGS {
Uint16 I2COAR;
union I2CIER_REG I2CIER;
union I2CSTR_REG I2CSTR;
Uint16 I2CCLKL;
Uint16 I2CCLKH;
Uint16 I2CCNT;
Uint16 I2CDRR;
Uint16 I2CSAR;
Uint16 I2CDXR;
union I2CMDR_REG I2CMDR;
union I2CISRC_REG I2CISRC;
Uint16 rsvd1;
union I2CPSC_REG I2CPSC;
Uint16 rsvd2[19];
union I2CFFTX_REG I2CFFTX;
union I2CFFRX_REG I2CFFRX;
};
extern volatile struct I2C_REGS I2caRegs;
struct PIECTRL_BITS {
Uint16 ENPIE:1;
Uint16 PIEVECT:15;
};
union PIECTRL_REG {
Uint16 all;
struct PIECTRL_BITS bit;
};
struct PIEIER_BITS {
Uint16 INTx1:1;
Uint16 INTx2:1;
Uint16 INTx3:1;
Uint16 INTx4:1;
Uint16 INTx5:1;
Uint16 INTx6:1;
Uint16 INTx7:1;
Uint16 INTx8:1;
Uint16 rsvd:8;
};
union PIEIER_REG {
Uint16 all;
struct PIEIER_BITS bit;
};
struct PIEIFR_BITS {
Uint16 INTx1:1;
Uint16 INTx2:1;
Uint16 INTx3:1;
Uint16 INTx4:1;
Uint16 INTx5:1;
Uint16 INTx6:1;
Uint16 INTx7:1;
Uint16 INTx8:1;
Uint16 rsvd:8;
};
union PIEIFR_REG {
Uint16 all;
struct PIEIFR_BITS bit;
};
struct PIEACK_BITS {
Uint16 ACK1:1;
Uint16 ACK2:1;
Uint16 ACK3:1;
Uint16 ACK4:1;
Uint16 ACK5:1;
Uint16 ACK6:1;
Uint16 ACK7:1;
Uint16 ACK8:1;
Uint16 ACK9:1;
Uint16 ACK10:1;
Uint16 ACK11:1;
Uint16 ACK12:1;
Uint16 rsvd:4;
};
union PIEACK_REG {
Uint16 all;
struct PIEACK_BITS bit;
};
struct PIE_CTRL_REGS {
union PIECTRL_REG PIECTRL;
union PIEACK_REG PIEACK;
union PIEIER_REG PIEIER1;
union PIEIFR_REG PIEIFR1;
union PIEIER_REG PIEIER2;
union PIEIFR_REG PIEIFR2;
union PIEIER_REG PIEIER3;
union PIEIFR_REG PIEIFR3;
union PIEIER_REG PIEIER4;
union PIEIFR_REG PIEIFR4;
union PIEIER_REG PIEIER5;
union PIEIFR_REG PIEIFR5;
union PIEIER_REG PIEIER6;
union PIEIFR_REG PIEIFR6;
union PIEIER_REG PIEIER7;
union PIEIFR_REG PIEIFR7;
union PIEIER_REG PIEIER8;
union PIEIFR_REG PIEIFR8;
union PIEIER_REG PIEIER9;
union PIEIFR_REG PIEIFR9;
union PIEIER_REG PIEIER10;
union PIEIFR_REG PIEIFR10;
union PIEIER_REG PIEIER11;
union PIEIFR_REG PIEIFR11;
union PIEIER_REG PIEIER12;
union PIEIFR_REG PIEIFR12;
};
extern volatile struct PIE_CTRL_REGS PieCtrlRegs;
typedef interrupt void(*PINT)(void);
struct PIE_VECT_TABLE {
PINT PIE1_RESERVED;
PINT PIE2_RESERVED;
PINT PIE3_RESERVED;
PINT PIE4_RESERVED;
PINT PIE5_RESERVED;
PINT PIE6_RESERVED;
PINT PIE7_RESERVED;
PINT PIE8_RESERVED;
PINT PIE9_RESERVED;
PINT PIE10_RESERVED;
PINT PIE11_RESERVED;
PINT PIE12_RESERVED;
PINT PIE13_RESERVED;
PINT XINT13;
PINT TINT2;
PINT DATALOG;
PINT RTOSINT;
PINT EMUINT;
PINT XNMI;
PINT ILLEGAL;
PINT USER1;
PINT USER2;
PINT USER3;
PINT USER4;
PINT USER5;
PINT USER6;
PINT USER7;
PINT USER8;
PINT USER9;
PINT USER10;
PINT USER11;
PINT USER12;
PINT SEQ1INT;
PINT SEQ2INT;
PINT rsvd1_3;
PINT XINT1;
PINT XINT2;
PINT ADCINT;
PINT TINT0;
PINT WAKEINT;
PINT EPWM1_TZINT;
PINT EPWM2_TZINT;
PINT EPWM3_TZINT;
PINT EPWM4_TZINT;
PINT EPWM5_TZINT;
PINT EPWM6_TZINT;
PINT rsvd2_7;
PINT rsvd2_8;
PINT EPWM1_INT;
PINT EPWM2_INT;
PINT EPWM3_INT;
PINT EPWM4_INT;
PINT EPWM5_INT;
PINT EPWM6_INT;
PINT rsvd3_7;
PINT rsvd3_8;
PINT ECAP1_INT;
PINT ECAP2_INT;
PINT ECAP3_INT;
PINT ECAP4_INT;
PINT rsvd4_5;
PINT rsvd4_6;
PINT rsvd4_7;
PINT rsvd4_8;
PINT EQEP1_INT;
PINT EQEP2_INT;
PINT rsvd5_3;
PINT rsvd5_4;
PINT rsvd5_5;
PINT rsvd5_6;
PINT rsvd5_7;
PINT rsvd5_8;
PINT SPIRXINTA;
PINT SPITXINTA;
PINT SPIRXINTB;
PINT SPITXINTB;
PINT SPIRXINTC;
PINT SPITXINTC;
PINT SPIRXINTD;
PINT SPITXINTD;
PINT rsvd7_1;
PINT rsvd7_2;
PINT rsvd7_3;
PINT rsvd7_4;
PINT rsvd7_5;
PINT rsvd7_6;
PINT rsvd7_7;
PINT rsvd7_8;
PINT I2CINT1A;
PINT I2CINT2A;
PINT rsvd8_3;
PINT rsvd8_4;
PINT rsvd8_5;
PINT rsvd8_6;
PINT rsvd8_7;
PINT rsvd8_8;
PINT SCIRXINTA;
PINT SCITXINTA;
PINT SCIRXINTB;
PINT SCITXINTB;
PINT ECAN0INTA;
PINT ECAN1INTA;
PINT ECAN0INTB;
PINT ECAN1INTB;
PINT rsvd10_1;
PINT rsvd10_2;
PINT rsvd10_3;
PINT rsvd10_4;
PINT rsvd10_5;
PINT rsvd10_6;
PINT rsvd10_7;
PINT rsvd10_8;
PINT rsvd11_1;
PINT rsvd11_2;
PINT rsvd11_3;
PINT rsvd11_4;
PINT rsvd11_5;
PINT rsvd11_6;
PINT rsvd11_7;
PINT rsvd11_8;
PINT rsvd12_1;
PINT rsvd12_2;
PINT rsvd12_3;
PINT rsvd12_4;
PINT rsvd12_5;
PINT rsvd12_6;
PINT rsvd12_7;
PINT rsvd12_8;
};
extern struct PIE_VECT_TABLE PieVectTable;
struct SPIFFTX_BITS {
Uint16 TXFFIL:5;
Uint16 TXFFIENA:1;
Uint16 TXFFINTCLR:1;
Uint16 TXFFINT:1;
Uint16 TXFFST:5;
Uint16 TXFIFO:1;
Uint16 SPIFFENA:1;
Uint16 SPIRST:1;
};
union SPIFFTX_REG {
Uint16 all;
struct SPIFFTX_BITS bit;
};
struct SPIFFRX_BITS {
Uint16 RXFFIL:5;
Uint16 RXFFIENA:1;
Uint16 RXFFINTCLR:1;
Uint16 RXFFINT:1;
Uint16 RXFFST:5;
Uint16 RXFIFORESET:1;
Uint16 RXFFOVFCLR:1;
Uint16 RXFFOVF:1;
};
union SPIFFRX_REG {
Uint16 all;
struct SPIFFRX_BITS bit;
};
struct SPIFFCT_BITS {
Uint16 TXDLY:8;
Uint16 rsvd:8;
};
union SPIFFCT_REG {
Uint16 all;
struct SPIFFCT_BITS bit;
};
struct SPICCR_BITS {
Uint16 SPICHAR:4;
Uint16 SPILBK:1;
Uint16 rsvd1:1;
Uint16 CLKPOLARITY:1;
Uint16 SPISWRESET:1;
Uint16 rsvd2:8;
};
union SPICCR_REG {
Uint16 all;
struct SPICCR_BITS bit;
};
struct SPICTL_BITS {
Uint16 SPIINTENA:1;
Uint16 TALK:1;
Uint16 MASTER_SLAVE:1;
Uint16 CLK_PHASE:1;
Uint16 OVERRUNINTENA:1;
Uint16 rsvd:11;
};
union SPICTL_REG {
Uint16 all;
struct SPICTL_BITS bit;
};
struct SPISTS_BITS {
Uint16 rsvd1:5;
Uint16 BUFFULL_FLAG:1;
Uint16 INT_FLAG:1;
Uint16 OVERRUN_FLAG:1;
Uint16 rsvd2:8;
};
union SPISTS_REG {
Uint16 all;
struct SPISTS_BITS bit;
};
struct SPIPRI_BITS {
Uint16 rsvd1:4;
Uint16 FREE:1;
Uint16 SOFT:1;
Uint16 PRIORITY:1;
Uint16 rsvd2:9;
};
union SPIPRI_REG {
Uint16 all;
struct SPIPRI_BITS bit;
};
struct SPI_REGS {
union SPICCR_REG SPICCR;
union SPICTL_REG SPICTL;
union SPISTS_REG SPISTS;
Uint16 rsvd1;
Uint16 SPIBRR;
Uint16 rsvd2;
Uint16 SPIRXEMU;
Uint16 SPIRXBUF;
Uint16 SPITXBUF;
Uint16 SPIDAT;
union SPIFFTX_REG SPIFFTX;
union SPIFFRX_REG SPIFFRX;
union SPIFFCT_REG SPIFFCT;
Uint16 rsvd3[2];
union SPIPRI_REG SPIPRI;
};
extern volatile struct SPI_REGS SpiaRegs;
extern volatile struct SPI_REGS SpibRegs;
extern volatile struct SPI_REGS SpicRegs;
extern volatile struct SPI_REGS SpidRegs;
struct SCICCR_BITS {
Uint16 SCICHAR:3;
Uint16 ADDRIDLE_MODE:1;
Uint16 LOOPBKENA:1;
Uint16 PARITYENA:1;
Uint16 PARITY:1;
Uint16 STOPBITS:1;
Uint16 rsvd1:8;
};
union SCICCR_REG {
Uint16 all;
struct SCICCR_BITS bit;
};
struct SCICTL1_BITS {
Uint16 RXENA:1;
Uint16 TXENA:1;
Uint16 SLEEP:1;
Uint16 TXWAKE:1;
Uint16 rsvd:1;
Uint16 SWRESET:1;
Uint16 RXERRINTENA:1;
Uint16 rsvd1:9;
};
union SCICTL1_REG {
Uint16 all;
struct SCICTL1_BITS bit;
};
struct SCICTL2_BITS {
Uint16 TXINTENA:1;
Uint16 RXBKINTENA:1;
Uint16 rsvd:4;
Uint16 TXEMPTY:1;
Uint16 TXRDY:1;
Uint16 rsvd1:8;
};
union SCICTL2_REG {
Uint16 all;
struct SCICTL2_BITS bit;
};
struct SCIRXST_BITS {
Uint16 rsvd:1;
Uint16 RXWAKE:1;
Uint16 PE:1;
Uint16 OE:1;
Uint16 FE:1;
Uint16 BRKDT:1;
Uint16 RXRDY:1;
Uint16 RXERROR:1;
};
union SCIRXST_REG {
Uint16 all;
struct SCIRXST_BITS bit;
};
struct SCIRXBUF_BITS {
Uint16 RXDT:8;
Uint16 rsvd:6;
Uint16 SCIFFPE:1;
Uint16 SCIFFFE:1;
};
union SCIRXBUF_REG {
Uint16 all;
struct SCIRXBUF_BITS bit;
};
struct SCIPRI_BITS {
Uint16 rsvd:3;
Uint16 FREE:1;
Uint16 SOFT:1;
Uint16 rsvd1:3;
};
union SCIPRI_REG {
Uint16 all;
struct SCIPRI_BITS bit;
};
struct SCIFFTX_BITS {
Uint16 TXFFIL:5;
Uint16 TXFFIENA:1;
Uint16 TXFFINTCLR:1;
Uint16 TXFFINT:1;
Uint16 TXFFST:5;
Uint16 TXFIFOXRESET:1;
Uint16 SCIFFENA:1;
Uint16 SCIRST:1;
};
union SCIFFTX_REG {
Uint16 all;
struct SCIFFTX_BITS bit;
};
struct SCIFFRX_BITS {
Uint16 RXFFIL:5;
Uint16 RXFFIENA:1;
Uint16 RXFFINTCLR:1;
Uint16 RXFFINT:1;
Uint16 RXFFST:5;
Uint16 RXFIFORESET:1;
Uint16 RXFFOVRCLR:1;
Uint16 RXFFOVF:1;
};
union SCIFFRX_REG {
Uint16 all;
struct SCIFFRX_BITS bit;
};
struct SCIFFCT_BITS {
Uint16 FFTXDLY:8;
Uint16 rsvd:5;
Uint16 CDC:1;
Uint16 ABDCLR:1;
Uint16 ABD:1;
};
union SCIFFCT_REG {
Uint16 all;
struct SCIFFCT_BITS bit;
};
struct SCI_REGS {
union SCICCR_REG SCICCR;
union SCICTL1_REG SCICTL1;
Uint16 SCIHBAUD;
Uint16 SCILBAUD;
union SCICTL2_REG SCICTL2;
union SCIRXST_REG SCIRXST;
Uint16 SCIRXEMU;
union SCIRXBUF_REG SCIRXBUF;
Uint16 rsvd1;
Uint16 SCITXBUF;
union SCIFFTX_REG SCIFFTX;
union SCIFFRX_REG SCIFFRX;
union SCIFFCT_REG SCIFFCT;
Uint16 rsvd2;
Uint16 rsvd3;
union SCIPRI_REG SCIPRI;
};
extern volatile struct SCI_REGS SciaRegs;
extern volatile struct SCI_REGS ScibRegs;
struct XCLK_BITS {
Uint16 XCLKOUTDIV:2;
Uint16 XCLKOUTDAT:1;
Uint16 X1DAT:1;
Uint16 XCLKINDAT:1;
Uint16 rsvd1:3;
Uint16 X1CNT:4;
Uint16 XCLKINCNT:4;
};
union XCLK_REG {
Uint16 all;
struct XCLK_BITS bit;
};
struct PLLSTS_BITS {
Uint16 PLLLOCKS:1;
Uint16 CLKINDIV:1;
Uint16 PLLOFF:1;
Uint16 MCLKSTS:1;
Uint16 MCLKCLR:1;
Uint16 OSCOFF:1;
Uint16 MCLKOFF:1;
Uint16 rsvd2:9;
};
union PLLSTS_REG {
Uint16 all;
struct PLLSTS_BITS bit;
};
struct HISPCP_BITS {
Uint16 HSPCLK:3;
Uint16 rsvd1:13;
};
union HISPCP_REG {
Uint16 all;
struct HISPCP_BITS bit;
};
struct LOSPCP_BITS {
Uint16 LSPCLK:3;
Uint16 rsvd1:13;
};
union LOSPCP_REG {
Uint16 all;
struct LOSPCP_BITS bit;
};
struct PCLKCR0_BITS {
Uint16 rsvd1:2;
Uint16 TBCLKSYNC:1;
Uint16 ADCENCLK:1;
Uint16 I2CAENCLK:1;
Uint16 rsvd2:1;
Uint16 SPICENCLK:1;
Uint16 SPIDENCLK:1;
Uint16 SPIAENCLK:1;
Uint16 SPIBENCLK:1;
Uint16 SCIAENCLK:1;
Uint16 SCIBENCLK:1;
Uint16 rsvd3:2;
Uint16 ECANAENCLK:1;
Uint16 ECANBENCLK:1;
};
union PCLKCR0_REG {
Uint16 all;
struct PCLKCR0_BITS bit;
};
struct PCLKCR1_BITS {
Uint16 EPWM1ENCLK:1;
Uint16 EPWM2ENCLK:1;
Uint16 EPWM3ENCLK:1;
Uint16 EPWM4ENCLK:1;
Uint16 EPWM5ENCLK:1;
Uint16 EPWM6ENCLK:1;
Uint16 rsvd1:2;
Uint16 ECAP1ENCLK:1;
Uint16 ECAP2ENCLK:1;
Uint16 ECAP3ENCLK:1;
Uint16 ECAP4ENCLK:1;
Uint16 rsvd2:2;
Uint16 EQEP1ENCLK:1;
Uint16 EQEP2ENCLK:1;
};
union PCLKCR1_REG {
Uint16 all;
struct PCLKCR1_BITS bit;
};
struct PLLCR_BITS {
Uint16 DIV:4;
Uint16 rsvd1:12;
};
union PLLCR_REG {
Uint16 all;
struct PLLCR_BITS bit;
};
struct LPMCR0_BITS {
Uint16 LPM:2;
Uint16 QUALSTDBY:6;
Uint16 rsvd1:7;
Uint16 WDINTE:1;
};
union LPMCR0_REG {
Uint16 all;
struct LPMCR0_BITS bit;
};
struct SCSR_BITS {
Uint16 WDOVERRIDE:1;
Uint16 WDENINT:1;
Uint16 rsvd1:14;
};
union SCSR_REG {
Uint16 all;
struct SCSR_BITS bit;
};
struct SYS_CTRL_REGS {
union XCLK_REG XCLK;
union PLLSTS_REG PLLSTS;
Uint16 rsvd1[8];
union HISPCP_REG HISPCP;
union LOSPCP_REG LOSPCP;
union PCLKCR0_REG PCLKCR0;
union PCLKCR1_REG PCLKCR1;
union LPMCR0_REG LPMCR0;
Uint16 rsvd2;
Uint16 rsvd3;
union PLLCR_REG PLLCR;
union SCSR_REG SCSR;
Uint16 WDCNTR;
Uint16 rsvd4;
Uint16 WDKEY;
Uint16 rsvd5[3];
Uint16 WDCR;
Uint16 rsvd6[6];
};
struct CSMSCR_BITS {
Uint16 SECURE:1;
Uint16 rsvd1:14;
Uint16 FORCESEC:1;
};
union CSMSCR_REG {
Uint16 all;
struct CSMSCR_BITS bit;
};
struct CSM_REGS {
Uint16 KEY0;
Uint16 KEY1;
Uint16 KEY2;
Uint16 KEY3;
Uint16 KEY4;
Uint16 KEY5;
Uint16 KEY6;
Uint16 KEY7;
Uint16 rsvd1;
Uint16 rsvd2;
Uint16 rsvd3;
Uint16 rsvd4;
Uint16 rsvd5;
Uint16 rsvd6;
Uint16 rsvd7;
union CSMSCR_REG CSMSCR;
};
struct CSM_PWL {
Uint16 PSWD0;
Uint16 PSWD1;
Uint16 PSWD2;
Uint16 PSWD3;
Uint16 PSWD4;
Uint16 PSWD5;
Uint16 PSWD6;
Uint16 PSWD7;
};
struct FOPT_BITS {
Uint16 ENPIPE:1;
Uint16 rsvd:15;
};
union FOPT_REG {
Uint16 all;
struct FOPT_BITS bit;
};
struct FPWR_BITS {
Uint16 PWR:2;
Uint16 rsvd:14;
};
union FPWR_REG {
Uint16 all;
struct FPWR_BITS bit;
};
struct FSTATUS_BITS {
Uint16 PWRS:2;
Uint16 STDBYWAITS:1;
Uint16 ACTIVEWAITS:1;
Uint16 rsvd1:4;
Uint16 V3STAT:1;
Uint16 rsvd2:7;
};
union FSTATUS_REG {
Uint16 all;
struct FSTATUS_BITS bit;
};
struct FSTDBYWAIT_BITS {
Uint16 STDBYWAIT:9;
Uint16 rsvd:7;
};
union FSTDBYWAIT_REG {
Uint16 all;
struct FSTDBYWAIT_BITS bit;
};
struct FACTIVEWAIT_BITS {
Uint16 ACTIVEWAIT:9;
Uint16 rsvd:7;
};
union FACTIVEWAIT_REG {
Uint16 all;
struct FACTIVEWAIT_BITS bit;
};
struct FBANKWAIT_BITS {
Uint16 RANDWAIT:4;
Uint16 rsvd1:4;
Uint16 PAGEWAIT:4;
Uint16 rsvd2:4;
};
union FBANKWAIT_REG {
Uint16 all;
struct FBANKWAIT_BITS bit;
};
struct FOTPWAIT_BITS {
Uint16 OTPWAIT:5;
Uint16 rsvd:11;
};
union FOTPWAIT_REG {
Uint16 all;
struct FOTPWAIT_BITS bit;
};
struct FLASH_REGS {
union FOPT_REG FOPT;
Uint16 rsvd1;
union FPWR_REG FPWR;
union FSTATUS_REG FSTATUS;
union FSTDBYWAIT_REG FSTDBYWAIT;
union FACTIVEWAIT_REG FACTIVEWAIT;
union FBANKWAIT_REG FBANKWAIT;
union FOTPWAIT_REG FOTPWAIT;
};
extern volatile struct SYS_CTRL_REGS SysCtrlRegs;
extern volatile struct CSM_REGS CsmRegs;
extern volatile struct CSM_PWL CsmPwl;
extern volatile struct FLASH_REGS FlashRegs;
struct XINTCR_BITS {
Uint16 ENABLE:1;
Uint16 rsvd1:1;
Uint16 POLARITY:2;
Uint16 rsvd2:12;
};
union XINTCR_REG {
Uint16 all;
struct XINTCR_BITS bit;
};
struct XNMICR_BITS {
Uint16 ENABLE:1;
Uint16 SELECT:1;
Uint16 POLARITY:2;
Uint16 rsvd2:12;
};
union XNMICR_REG {
Uint16 all;
struct XNMICR_BITS bit;
};
struct XINTRUPT_REGS {
union XINTCR_REG XINT1CR;
union XINTCR_REG XINT2CR;
Uint16 rsvd1[5];
union XNMICR_REG XNMICR;
Uint16 XINT1CTR;
Uint16 XINT2CTR;
Uint16 rsvd[5];
Uint16 XNMICTR;
};
extern volatile struct XINTRUPT_REGS XIntruptRegs;
extern void InitAdc(void);
extern void InitPeripherals(void);
extern void InitECan(void);
extern void InitECana(void);
extern void InitECanGpio(void);
extern void InitECanaGpio(void);
extern void InitECanb(void);
extern void InitECanbGpio(void);
extern void InitECap(void);
extern void InitECapGpio(void);
extern void InitECap1Gpio(void);
extern void InitECap2Gpio(void);
extern void InitECap3Gpio(void);
extern void InitECap4Gpio(void);
extern void InitEPwm(void);
extern void InitEPwmGpio(void);
extern void InitEPwm1Gpio(void);
extern void InitEPwm2Gpio(void);
extern void InitEPwm3Gpio(void);
extern void InitEPwm4Gpio(void);
extern void InitEPwm5Gpio(void);
extern void InitEPwm6Gpio(void);
extern void InitEQep(void);
extern void InitEQepGpio(void);
extern void InitEQep1Gpio(void);
extern void InitEQep2Gpio(void);
extern void InitGpio(void);
extern void InitI2CGpio(void);
extern void InitSci(void);
extern void InitSciGpio(void);
extern void InitSciaGpio(void);
extern void InitScibGpio(void);
extern void InitSpi(void);
extern void InitSpiGpio(void);
extern void InitSpiaGpio(void);
extern void InitSpibGpio(void);
extern void InitSpicGpio(void);
extern void InitSpidGpio(void);
extern void InitSysCtrl(void);
extern void InitTzGpio(void);
extern void InitXIntrupt(void);
extern void InitPll(Uint16 pllcr, Uint16 clkindiv);
extern void InitPeripheralClocks(void);
extern void EnableInterrupts(void);
extern void DSP28x_usDelay(Uint32 Count);
extern void ServiceDog(void);
extern void DisableDog(void);
extern void SetDBGIER(Uint16 dbgier);
extern void InitFlash(void);
void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr);
extern Uint16 RamfuncsLoadStart;
extern Uint16 RamfuncsLoadEnd;
extern Uint16 RamfuncsRunStart;
struct I2CMSG {
Uint16 MsgStatus;
Uint16 SlaveAddress;
Uint16 NumOfBytes;
Uint16 MemoryHighAddr;
Uint16 MemoryLowAddr;
Uint16 MsgBuffer[16];
};
typedef unsigned char Uint8;
typedef long long int64;
typedef unsigned long long Uint64;
typedef unsigned int BOOL;
typedef unsigned char BYTE;
typedef int SWORD;
typedef unsigned int WORD;
typedef long SLONG;
typedef unsigned long LONG;
extern void ioInit(void);
WORD wTest1, wTest2;
void mainInit(void)
{
ioInit();
}
void main()
{
mainInit();
asm(" clrc INTM");
while (1){
wTest1 = EPwm1Regs.TBCTR;
wTest2 = EPwm1Regs . TBPRD;
}
}
void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr);
interrupt void PIE_RESERVED(void);
extern interrupt void scia_tx_isr(void);
extern interrupt void scia_rx_isr(void);
interrupt void ADC_ISR(void);
void InitPieCtrl(void)
{
PieCtrlRegs.PIECTRL.bit.ENPIE = 0;
PieCtrlRegs.PIEIER1.all = 0;
PieCtrlRegs.PIEIER2.all = 0;
PieCtrlRegs.PIEIER3.all = 0;
PieCtrlRegs.PIEIER4.all = 0;
PieCtrlRegs.PIEIER5.all = 0;
PieCtrlRegs.PIEIER6.all = 0;
PieCtrlRegs.PIEIER7.all = 0;
PieCtrlRegs.PIEIER8.all = 0;
PieCtrlRegs.PIEIER9.all = 0;
PieCtrlRegs.PIEIER10.all = 0;
PieCtrlRegs.PIEIER11.all = 0;
PieCtrlRegs.PIEIER12.all = 0;
PieCtrlRegs.PIEIFR1.all = 0;
PieCtrlRegs.PIEIFR2.all = 0;
PieCtrlRegs.PIEIFR3.all = 0;
PieCtrlRegs.PIEIFR4.all = 0;
PieCtrlRegs.PIEIFR5.all = 0;
PieCtrlRegs.PIEIFR6.all = 0;
PieCtrlRegs.PIEIFR7.all = 0;
PieCtrlRegs.PIEIFR8.all = 0;
PieCtrlRegs.PIEIFR9.all = 0;
PieCtrlRegs.PIEIFR10.all = 0;
PieCtrlRegs.PIEIFR11.all = 0;
PieCtrlRegs.PIEIFR12.all = 0;
PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
PieCtrlRegs.PIEIER1.bit.INTx1 = 1;
PieCtrlRegs.PIEIER9.bit.INTx1 = 1;
PieCtrlRegs.PIEIER9.bit.INTx2 = 1;
PieCtrlRegs.PIECTRL.bit.ENPIE = 1;
PieCtrlRegs.PIEACK.all = 0xFFFF;
}
interrupt void SWT_250US_ISR(void) ;
void InitPieVectTable(void)
{
int16 i;
Uint32 *Dest = (void *) &PieVectTable;
asm(" EALLOW");
for(i=0; i < 128; i++) {
*Dest++ = (Uint32)&PIE_RESERVED;
}
asm(" EDIS");
asm(" EALLOW");
PieVectTable.TINT0 = &SWT_250US_ISR;
PieVectTable.SEQ1INT = &ADC_ISR;
PieVectTable.SCIRXINTA = &scia_rx_isr;
PieVectTable.SCITXINTA = &scia_tx_isr;
asm(" EDIS");
}
void EnablePeripheral(void)
{
asm(" clrc DBGM");
IER |= ( 0x0001 |
0x0100
);
IFR = 0x0000;
}
interrupt void PIE_RESERVED(void)
{
asm (" ESTOP0");
for(;;);
}
WORD wWDCNTR;
WORD wWDCNTRMax;
void clrWdog(void)
{
asm(" EALLOW");
SysCtrlRegs.WDKEY = 0x55;
SysCtrlRegs.WDKEY = 0xaa;
asm(" EDIS");
}
WORD wWDCNTR1, wWDCNTR2;
extern WORD spiTxIdx, serialDaData[4];
void InitGpio(void){
asm(" EALLOW");
GpioCtrlRegs.GPAMUX2.bit.GPIO28 = 1;
GpioCtrlRegs.GPAPUD.bit.GPIO28 = 0;
GpioCtrlRegs.GPAMUX2.bit.GPIO29 = 1;
GpioCtrlRegs.GPAPUD.bit.GPIO29 = 0;
GpioCtrlRegs.GPBMUX1.bit.GPIO34 = 0;
GpioCtrlRegs.GPBDIR.bit.GPIO34 = 0;
GpioCtrlRegs.GPACTRL.bit.QUALPRD1 = 0x02;
asm(" EDIS");
}
WORD wPwmSample;
WORD wTest3, wTest4;
void InitEPwm(void)
{
asm(" EALLOW");
GpioCtrlRegs.GPAPUD.bit.GPIO0 = 0;
GpioCtrlRegs.GPAPUD.bit.GPIO1 = 0;
GpioCtrlRegs.GPAPUD.bit.GPIO2 = 0;
GpioCtrlRegs.GPAPUD.bit.GPIO3 = 0;
GpioCtrlRegs.GPAPUD.bit.GPIO4 = 0;
GpioCtrlRegs.GPAPUD.bit.GPIO5 = 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO0 = 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO1 = 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO2 = 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO3 = 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO4 = 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO5 = 0;
GpioCtrlRegs.GPAMUX1.bit.GPIO12 = 1;
GpioCtrlRegs.GPAMUX1.bit.GPIO13 = 1;
GpioCtrlRegs.GPAMUX1.bit.GPIO14 = 1;
GpioCtrlRegs.GPAMUX1.bit.GPIO15 = 1;
GpioCtrlRegs.GPAQSEL1.bit.GPIO12 = 1;
GpioCtrlRegs.GPAQSEL1.bit.GPIO13 = 1;
GpioCtrlRegs.GPAQSEL1.bit.GPIO14 = 1;
GpioCtrlRegs.GPAQSEL1.bit.GPIO15 = 1;
EPwm1Regs.TZSEL.bit.CBC1 = 1;
EPwm1Regs.TZSEL.bit.OSHT2 = 1;
EPwm1Regs.TZSEL.bit.OSHT3 = 1;
EPwm1Regs.TZSEL.bit.OSHT4 = 1;
EPwm1Regs.TZEINT.bit.CBC = 1;
EPwm1Regs.TZEINT.bit.OST = 1;
EPwm2Regs.TZSEL.bit.CBC1 = 1;
EPwm2Regs.TZSEL.bit.OSHT2 = 1;
EPwm2Regs.TZSEL.bit.OSHT3 = 1;
EPwm2Regs.TZSEL.bit.OSHT4 = 1;
EPwm2Regs.TZEINT.bit.CBC = 1;
EPwm2Regs.TZEINT.bit.OST = 1;
EPwm3Regs.TZSEL.bit.CBC1 = 1;
EPwm3Regs.TZSEL.bit.OSHT2 = 1;
EPwm3Regs.TZSEL.bit.OSHT3 = 1;
EPwm3Regs.TZSEL.bit.OSHT4 = 1;
EPwm3Regs.TZEINT.bit.CBC = 1;
EPwm3Regs.TZEINT.bit.OST = 1;
EPwm1Regs.TZCLR.bit.CBC = 1;
EPwm2Regs.TZCLR.bit.CBC = 1;
EPwm3Regs.TZCLR.bit.CBC = 1;
EPwm1Regs.TZCLR.bit.OST = 1;
EPwm2Regs.TZCLR.bit.OST = 1;
EPwm3Regs.TZCLR.bit.OST = 1;
EPwm1Regs.TZCLR.bit.INT = 1;
EPwm2Regs.TZCLR.bit.INT = 1;
EPwm3Regs.TZCLR.bit.INT = 1;
EPwm1Regs.TZCTL.bit.TZA = 0x1;
EPwm1Regs.TZCTL.bit.TZB = 0x1;
EPwm2Regs.TZCTL.bit.TZA = 0x1;
EPwm2Regs.TZCTL.bit.TZB = 0x1;
EPwm3Regs.TZCTL.bit.TZA = 0x1;
EPwm3Regs.TZCTL.bit.TZB = 0x1;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
asm(" EDIS");
EPwm1Regs.TBPHS.half.TBPHS = 0;
EPwm1Regs.TBCTL.bit.FREE_SOFT = 2;
EPwm1Regs.TBCTL.bit.CTRMODE = 0x2;
EPwm1Regs.TBCTL.bit.PHSEN = 0x0;
EPwm1Regs.TBCTL.bit.PRDLD = 0x0;
EPwm1Regs.TBCTL.bit.SYNCOSEL = 0x1;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0x0;
EPwm1Regs.CMPCTL.bit.SHDWBMODE = 0x0;
EPwm1Regs.CMPCTL.bit.LOADAMODE = 0x0;
EPwm1Regs.CMPCTL.bit.LOADBMODE = 0x0;
EPwm1Regs.AQCTLA.bit.CBU = 0x1;
EPwm1Regs.AQCTLA.bit.CAD = 0x2;
EPwm1Regs.DBCTL.bit.OUT_MODE = 0x3;
EPwm1Regs.DBCTL.bit.POLSEL = 0x1;
EPwm1Regs.DBFED = 75;
EPwm1Regs.DBRED = 75;
EPwm1Regs.ETSEL.bit.INTSEL = 0x1;
EPwm1Regs.ETSEL.bit.INTEN = 1;
EPwm1Regs.ETPS.bit.INTPRD = 0x1;
EPwm2Regs.TBPHS.half.TBPHS = 0;
EPwm2Regs.TBCTL.bit.FREE_SOFT = 2;
EPwm2Regs.TBCTL.bit.CTRMODE = 0x2;
EPwm2Regs.TBCTL.bit.PHSEN = 0x1;
EPwm2Regs.TBCTL.bit.PRDLD = 0x0;
EPwm2Regs.TBCTL.bit.SYNCOSEL = 0x0;
EPwm2Regs.CMPCTL.bit.SHDWAMODE = 0x0;
EPwm2Regs.CMPCTL.bit.SHDWBMODE = 0x0;
EPwm2Regs.CMPCTL.bit.LOADAMODE = 0x0;
EPwm2Regs.CMPCTL.bit.LOADBMODE = 0x0;
EPwm2Regs.AQCTLA.bit.CBU = 0x1;
EPwm2Regs.AQCTLA.bit.CAD = 0x2;
EPwm2Regs.DBCTL.bit.OUT_MODE = 0x3;
EPwm2Regs.DBCTL.bit.POLSEL = 0x1;
EPwm2Regs.DBFED = 75;
EPwm2Regs.DBRED = 75;
EPwm3Regs.TBPHS.half.TBPHS = 0;
EPwm3Regs.TBCTL.bit.FREE_SOFT = 2;
EPwm3Regs.TBCTL.bit.CTRMODE = 0x2;
EPwm3Regs.TBCTL.bit.PHSEN = 0x1;
EPwm3Regs.TBCTL.bit.PRDLD = 0x0;
EPwm3Regs.TBCTL.bit.SYNCOSEL = 0x0;
EPwm3Regs.CMPCTL.bit.SHDWAMODE = 0x0;
EPwm3Regs.CMPCTL.bit.SHDWBMODE = 0x0;
EPwm3Regs.CMPCTL.bit.LOADAMODE = 0x0;
EPwm3Regs.CMPCTL.bit.LOADBMODE = 0x0;
EPwm3Regs.AQCTLA.bit.CBU = 0x1;
EPwm3Regs.AQCTLA.bit.CAD = 0x2;
EPwm3Regs.DBCTL.bit.OUT_MODE = 0x3;
EPwm3Regs.DBCTL.bit.POLSEL = 0x1;
EPwm3Regs.DBFED = 75;
EPwm3Regs.DBRED = 75;
EPwm1Regs . TBPRD = (5000);
EPwm2Regs . TBPRD = (5000);
EPwm3Regs . TBPRD = (5000);
wTest3 = EPwm1Regs . TBPRD;
wTest4 = 100;
EPwm4Regs . CMPA . half . CMPA = (5000);
EPwm4Regs . TBPRD = (5000);
wPwmSample = (5000) - 1;
EPwm4Regs.CMPA.half.CMPA = (5000);
EPwm4Regs.TBPHS.half.TBPHS = 0;
EPwm4Regs.TBCTR = 0;
EPwm4Regs.TBCTL.bit.CTRMODE = 0x2;
EPwm4Regs.TBCTL.bit.PHSEN = 0x1;
EPwm4Regs.TBCTL.bit.PRDLD = 0x0;
EPwm4Regs.TBCTL.bit.SYNCOSEL = 0x0;
EPwm4Regs.ETSEL.bit.INTSEL = 0x2;
EPwm4Regs.ETSEL.bit.INTEN = 0;
EPwm4Regs.ETPS.bit.INTPRD = 0x1;
EPwm4Regs.ETSEL.bit.SOCAEN = 1;
EPwm4Regs.ETSEL.bit.SOCBEN = 0;
EPwm4Regs.ETSEL.bit.SOCASEL = 0x2;
EPwm4Regs.CMPCTL.bit.LOADAMODE = 0x0;
EPwm4Regs.ETPS.bit.SOCAPRD = 0x1;
EPwm1Regs.ETSEL.bit.SOCAEN = 0;
EPwm2Regs.ETSEL.bit.SOCAEN = 0;
EPwm3Regs.ETSEL.bit.SOCAEN = 0;
EPwm1Regs.ETSEL.bit.SOCBEN = 0;
EPwm2Regs.ETSEL.bit.SOCBEN = 0;
EPwm3Regs.ETSEL.bit.SOCBEN = 0;
asm(" EALLOW");
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
asm(" EDIS");
}
void InitAdc(void);
void CommInitSerial (void);
void InitCpuTimer0(void);
void ioInit(void)
{
asm(" setc INTM");
IER = 0x0000;
IFR = 0x0000;
InitSysCtrl();
MemCopy(&RamfuncsLoadStart, &RamfuncsLoadEnd, &RamfuncsRunStart);
InitFlash();
InitGpio();
InitEPwm();
InitCpuTimer0();
(CpuTimer0Regs . TCR . bit . TSS = 0);
InitPieVectTable();
InitPieCtrl();
InitAdc();
EnablePeripheral();
CommInitSerial();
}
void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr)
{
while(SourceAddr < SourceEndAddr)
{
*DestAddr++ = *SourceAddr++;
}
return;
}
WORD wTestISR1, wTestISR2, wTestISR3, wTestISR4, wTestISR5, wTestISR6, wTestISR7, wTestISR8, wTestISR9, wTestISR10, wTestISR11;
typedef struct {
SWORD *ch1; SWORD *ch2;
}
adType;
WORD wIasADRaw, wIbsADRaw, wIcsADRaw;
WORD wNtcOutAD, wVdcAD, wNtcOutAD2;
static const adType adTbl[] = {
{(SWORD *)&wIasADRaw, (SWORD *)&wIcsADRaw},
{(SWORD *)&wIbsADRaw, (SWORD *)&wVdcAD},
{(SWORD *)&wNtcOutAD, (SWORD *)&wNtcOutAD2}
};
SWORD iIasAD, iIbsAD, iIcsAD, iIas, iIbs, iIcs, iDirOfCT, iIasOffset, iIbs0, iIbsOffset, iIcsOffset;
WORD fSecondGroup;
WORD wADConvCompleted, wADConvCntADISR;
interrupt void ADC_ISR(void)
{
Uint16 nCh;
Uint16 *pStartAddr;
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
IER |= 0x0001;
IER &= (0xFFFF & ~(1 << 1) & ~(1 << 2) & ~(1 << 3) & ~(1 << 4) & ~(1 << 5) & ~(1 << 6) & ~(1 << 7) & ~(1 << 8) & ~(1 << 9) & ~(1 << 10) & ~(1 << 11) & ~(1 << 12) & ~(1 << 13) & ~(1 << 14) & ~(1 << 15));
PieCtrlRegs.PIEIER1.all &= (0x00FE & ~(1 << 1) & ~(1 << 2) & ~(1 << 3) & ~(1 << 4) & ~(1 << 5) & ~(1 << 6) & ~(1 << 7));
PieCtrlRegs.PIEACK.all = 0xFFFF;
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1;
AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;
wTestISR7++;
wTestISR9 = EPwm4Regs.TBCTR;
if(wTestISR7 > 1) {
wTestISR8++;
wTestISR10 = wTestISR9;
}
asm(" clrc INTM");
pStartAddr = (Uint16 *)&(AdcRegs.ADCRESULT0);
for(nCh = 0; nCh < 3; nCh++) {
*adTbl[nCh].ch1 = (*(pStartAddr + nCh*2));
*adTbl[nCh].ch2 = (*(pStartAddr + nCh*2 + 1));
}
iIasAD = (SWORD)((WORD)wIasADRaw - (WORD)((WORD)(0x8000)));
iIbsAD = (SWORD)((WORD)wIbsADRaw - (WORD)((WORD)(0x8000)));
iIcsAD = (SWORD)((WORD)wIcsADRaw - (WORD)((WORD)(0x8000)));
asm(" setc INTM");
asm(" SETC OVM ");;
if(fSecondGroup == 0) {
iIas = iDirOfCT * ((((SLONG)iIasAD << 16) - ((SLONG)iIasOffset << 16)) >> 16);
iIbs0 = iDirOfCT * ((((SLONG)iIbsAD << 16) - ((SLONG)iIbsOffset << 16)) >> 16);
iIcs = iDirOfCT * ((((SLONG)iIcsAD << 16) - ((SLONG)iIcsOffset << 16)) >> 16);
iIbs = -((SLONG)iIas + iIcs);
}
wADConvCompleted = 1;
wADConvCntADISR++;
asm(" CLRC OVM ");;
asm(" clrc INTM");
wTestISR7 = 0;
asm(" setc INTM");
PieCtrlRegs.PIEIER1.all = TempPIEIER;
}
void adcInitOffset(void)
{
AdcRegs.ADCTRL3.all = 0x00C0;
DSP28x_usDelay(((((long double) 12000L * 1000.0L) / (long double)16.667L) - 9.0L) / 5.0L);
AdcRegs.ADCTRL3.bit.ADCPWDN = 1;
DSP28x_usDelay(((((long double) 1000L * 1000.0L) / (long double)16.667L) - 9.0L) / 5.0L);
AdcRegs.ADCTRL3.bit.SMODE_SEL = 0;
AdcRegs.ADCTRL1.bit.ACQ_PS = 7;
AdcRegs.ADCTRL1.bit.CPS = 0;
AdcRegs.ADCTRL1.bit.SUSMOD = 2;
AdcRegs.ADCTRL3.bit.ADCCLKPS = 1;
AdcRegs.ADCMAXCONV.all = 0x0004;
AdcRegs.ADCTRL1.bit.SEQ_CASC = 1;
AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0;
AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x8;
AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 0x1;
AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 0x9;
AdcRegs.ADCCHSELSEQ2.bit.CONV04 = 0x3;
AdcRegs.ADCTRL1.bit.CONT_RUN = 0;
AdcRegs.ADCTRL2.all = 0x4040;
}
WORD wVdcRef, wInvCapADVal;
void adcoffsetread(void)
{
SLONG a, b, c;
LONG d, e, f;
WORD i;
a = b = c = 0L;
d = e = f = 0L;
adcInitOffset();
for(i = 0; i < 5; i++) {
DSP28x_usDelay(((((long double) 1000L * 1000.0L) / (long double)16.667L) - 9.0L) / 5.0L);
clrWdog();
}
for(i = 0; i < (1<<10); i++) {
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1;
AdcRegs.ADCTRL2.bit.SOC_SEQ1 = 1;
while (AdcRegs.ADCST.bit.SEQ1_BSY == 1) {;}
DSP28x_usDelay(((((long double) 10L * 1000.0L) / (long double)16.667L) - 9.0L) / 5.0L);
AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;
a += AdcRegs.ADCRESULT0;
b += AdcRegs.ADCRESULT1;
c += AdcRegs.ADCRESULT2;
d += AdcRegs.ADCRESULT3;
e += AdcRegs.ADCRESULT4;
f += AdcRegs.ADCRESULT5;
}
iIasOffset = (SWORD)(a>>10);
iIcsOffset = (SWORD)(b>>10);
iIbsOffset = (SWORD)(c>>10);
iIasOffset = (SWORD)((WORD)iIasOffset - (WORD)((WORD)(0x8000)));
iIbsOffset = (SWORD)((WORD)iIbsOffset - (WORD)((WORD)(0x8000)));
iIcsOffset = (SWORD)((WORD)iIcsOffset - (WORD)((WORD)(0x8000)));
wVdcRef = (d >> 10);
wInvCapADVal = (e >> 10);
wNtcOutAD2= (f >> 10);
}
void adcInit(void)
{
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1;
AdcRegs.ADCTRL3.bit.SMODE_SEL = 1;
AdcRegs.ADCTRL1.bit.ACQ_PS = 4;
AdcRegs.ADCTRL1.bit.CPS = 0;
AdcRegs.ADCTRL1.bit.SUSMOD = 2;
AdcRegs.ADCTRL3.bit.ADCCLKPS = 1;
AdcRegs.ADCMAXCONV.all = 0x0002;
AdcRegs.ADCTRL1.bit.SEQ_CASC = 1;
AdcRegs.ADCTRL1.bit.CONT_RUN = 0;
AdcRegs.ADCCHSELSEQ1.all = 0x0210;
AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1;
}
void InitAdc(void)
{
adcoffsetread();
adcInit();
}
WORD wTest5;
interrupt void SWT_250US_ISR(void)
{
volatile Uint16 TempPIEIER = PieCtrlRegs.PIEIER1.all;
IER |= 0x0001;
IER &= (0xFFFF & ~(1 << 1) & ~(1 << 2) & ~(1 << 3) & ~(1 << 4) & ~(1 << 5) & ~(1 << 6) & ~(1 << 7) & ~(1 << 8) & ~(1 << 9) & ~(1 << 10) & ~(1 << 11) & ~(1 << 12) & ~(1 << 13) & ~(1 << 14) & ~(1 << 15));
PieCtrlRegs.PIEIER1.all &= (0xFFFF & ~(1 << 1) & ~(1 << 2) & ~(1 << 3) & ~(1 << 4) & ~(1 << 5) & 0x00BF & ~(1 << 7));
PieCtrlRegs.PIEACK.all = 0xFFFF;
asm(" clrc INTM");
wTest5++;
asm(" setc INTM");
PieCtrlRegs.PIEIER1.all = TempPIEIER;
}
struct CPUTIMER_VARS CpuTimer0;
void InitCpuTimer0(void)
{
CpuTimer0.RegsAddr = &CpuTimer0Regs;
CpuTimer0Regs.PRD.all = 0xFFFFFFFF;
CpuTimer0Regs.TPR.all = 0;
CpuTimer0Regs.TPRH.all = 0;
CpuTimer0Regs.TCR.bit.TSS = 1;
CpuTimer0Regs.TCR.bit.TRB = 1;
CpuTimer0.InterruptCount = 0;
CpuTimer0.CPUFreqInMHz = 60;
CpuTimer0.PeriodInUSec = 60000;
CpuTimer0Regs.PRD.all = 15000;
CpuTimer0Regs.TPR.all = 0;
CpuTimer0Regs.TPRH.all = 0;
CpuTimer0Regs.TCR.bit.TSS = 1;
CpuTimer0Regs.TCR.bit.TRB = 1;
CpuTimer0Regs.TCR.bit.SOFT = 1;
CpuTimer0Regs.TCR.bit.FREE = 1;
CpuTimer0Regs.TCR.bit.TIE = 1;
}
