CCS/TMS320F28035: Adopting CLA into TMDSSOLAREXPKIT

Thank you, it helps, and now I can build the project, but another issue appears. I try to inspire with other project, when I configure, yhe CLA, but after I run the project, none of the register has changed. I create variable 'trstCLA', for debugging purpos and to observe is the program going into the Cla tasks. I did the followisng changes:

I create the CLA_Shared.h file:

/*
 * CLA_Shared.h
 *
 *  Created on: Nov 16, 2020
 *      Author: krysik
 */
#ifndef CLASHARED_C_H_
#define CLASHARED_C_H_



#ifdef __TMS320C28XX__
#define C28x_volatile volatile
#else
#define C28x_volatile
#endif

#ifndef DSP28_DATA_TYPES
#define DSP28_DATA_TYPES
typedef short           int16;
typedef long            int32;
typedef unsigned short  Uint16;
typedef unsigned long   Uint32;
typedef float           float32;
typedef long double     float64;
#endif


#include "SINEANALYZER_DIFF_wPWR_CLA.h"
#include "DSP2803x_Adc.h"
#include "DSP28x_Project.h"

extern int16 testCLA;

//CLA C Tasks defined in Cla1Tasks_C.cla
interrupt void Cla1Task1();
interrupt void Cla1Task2();
interrupt void Cla1Task3();
interrupt void Cla1Task4();
interrupt void Cla1Task5();
interrupt void Cla1Task6();
interrupt void Cla1Task7();
interrupt void Cla1Task8();

#endif /* CLA_SHARED_H_ */

I create claTasks.cla file:

#include "CLA_Shared.h"
#pragma DATA_SECTION(testCLA,"Cla1ToCpuMsgRAM");
int16 testCLA;

interrupt void Cla1Task1(void) {
    testCLA=4;
}

interrupt void Cla1Task2 ( void ){}
interrupt void Cla1Task3 ( void ){}
interrupt void Cla1Task4 ( void ){}
interrupt void Cla1Task5 ( void ){}
interrupt void Cla1Task6 ( void ){}
interrupt void Cla1Task7 ( void )

interrupt void Cla1Task8(void) 
{testCLA=2;}

In the SolarExplorer-DevInit_F2803x I uncomment the Cla _init and some register changes:

void CLA_Init()
{ 
   // This code assumes the CLA clock is already enabled in 
   // the call to DevInit();
   //
   // EALLOW: is needed to write to EALLOW protected registers
   // EDIS: is needed to disable write to EALLOW protected registers
   //
   // The symbols used in this calculation are defined in the CLA 
   // assembly code and in the CLAShared.h header file

//   EALLOW;
//   Cla1Regs.MVECT1 = (Uint16) (&Cla1Task1 - &Cla1Prog_Start)*sizeof(Uint32);
//   Cla1Regs.MVECT2 = (Uint16) (&Cla1Task2 - &Cla1Prog_Start)*sizeof(Uint32);
//   Cla1Regs.MVECT3 = (Uint16) (&Cla1Task3 - &Cla1Prog_Start)*sizeof(Uint32);
//   Cla1Regs.MVECT4 = (Uint16) (&Cla1Task4 - &Cla1Prog_Start)*sizeof(Uint32);
//   Cla1Regs.MVECT5 = (Uint16) (&Cla1Task5 - &Cla1Prog_Start)*sizeof(Uint32);
//   Cla1Regs.MVECT6 = (Uint16) (&Cla1Task6 - &Cla1Prog_Start)*sizeof(Uint32);
//   Cla1Regs.MVECT7 = (Uint16) (&Cla1Task7 - &Cla1Prog_Start)*sizeof(Uint32);
//   Cla1Regs.MVECT8 = (Uint16) (&Cla1Task8 - &Cla1Prog_Start)*sizeof(Uint32);

    EALLOW;
    Cla1Regs.MVECT1 = ((Uint16)Cla1Task1 - (Uint16)&Cla1Prog_Start);
    Cla1Regs.MVECT2 = ((Uint16)Cla1Task2 - (Uint16)&Cla1Prog_Start);
    Cla1Regs.MVECT3 = ((Uint16)Cla1Task3 - (Uint16)&Cla1Prog_Start);
    Cla1Regs.MVECT4 = ((Uint16)Cla1Task4 - (Uint16)&Cla1Prog_Start);
    Cla1Regs.MVECT5 = ((Uint16)Cla1Task5 - (Uint16)&Cla1Prog_Start);
    Cla1Regs.MVECT6 = ((Uint16)Cla1Task6 - (Uint16)&Cla1Prog_Start);
    Cla1Regs.MVECT7 = ((Uint16)Cla1Task7 - (Uint16)&Cla1Prog_Start);
    Cla1Regs.MVECT8 = ((Uint16)Cla1Task8 - (Uint16)&Cla1Prog_Start);

    //--- Select Task interrupt sources
        Cla1Regs.MPISRCSEL1.bit.PERINT1SEL = 0; // 0=ADCINT1    1=none    2=EPWM1INT
        Cla1Regs.MPISRCSEL1.bit.PERINT2SEL = 1; // 0=ADCINT2    1=none    2=EPWM2INT
        Cla1Regs.MPISRCSEL1.bit.PERINT3SEL = 1; // 0=ADCINT3    1=none    2=EPWM3INT
        Cla1Regs.MPISRCSEL1.bit.PERINT4SEL = 1; // 0=ADCINT4    1=none    2=EPWM4INT
        Cla1Regs.MPISRCSEL1.bit.PERINT5SEL = 1; // 0=ADCINT5    1=none    2=EPWM5INT
        Cla1Regs.MPISRCSEL1.bit.PERINT6SEL = 1; // 0=ADCINT6    1=none    2=EPWM6INT
        Cla1Regs.MPISRCSEL1.bit.PERINT7SEL = 1; // 0=ADCINT7    1=none    2=EPWM7INT
        Cla1Regs.MPISRCSEL1.bit.PERINT8SEL = 1; // 0=ADCINT8    1=none    2=CPU Timer 0
   // Copy the CLA program code from its load address to the CLA program memory
   // Once done, assign the program memory to the CLA
   //
   // Make sure there are at least two SYSCLKOUT cycles between assigning
   // the memory to the CLA and when an interrupt comes in
   // Call this function even if Load and Run address is the same!   
   MemCopy(&Cla1funcsLoadStart, &Cla1funcsLoadEnd, &Cla1funcsRunStart); 


	asm("   RPT #3 || NOP");
	 
	Cla1Regs.MMEMCFG.bit.PROGE = 1;		// Configure the RAM as CLA program memory
//	Cla1Regs.MMEMCFG .bit.RAM0E = 1;     // configure RAM L1, F28035 as CLA Data memory 0
//	Cla1Regs.MMEMCFG.bit.RAM1E = 1;		// Configure RAM L2, F28035 as CLA data memory 1

	    
   // Enable the IACK instruction to start a task
   // Enable the CLA interrupt 8 and interrupt 2
   	asm("   RPT #3 || NOP"); 
   	     
   Cla1Regs.MCTL.bit.IACKE = 1;
   Cla1Regs.MIER.all = 0x0001;// M_INT8;
 
   // No need to wait, the task will finish by the time
   // we configure the ePWM and ADC modules
  	Cla1ForceTask8(); 
	EDIS;
	//--- Enable the CLA interrupt
	EALLOW;
	    PieCtrlRegs.PIEIER11.bit.INTx1 = 1; // Enable CLA Task1 in PIE group #11
	    IER |= 0x0400;                      // Enable INT11 in IER to enable PIE group 11
	    Cla1Regs.MIER.all = (M_INT1 |M_INT8);
	            asm("   RPT #3 || NOP");
	            EDIS;
}	

And finally in the F28035_FLASH_SolarExplorer.CMD 

_Cla1Prog_Start = _Cla1funcsRunStart;
--undef_sym=__cla_scratchpad_end
--undef_sym=__cla_scratchpad_start

MEMORY
{
/* Note that the memory allocation below does not create sections as necessary for
   the CLA on the F2803x. 
*/

PAGE 0:
	
	RAML3	    : origin = 0x009000, length = 0x001000     /* data RAM (L3) */
	OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */
	FLASHH      : origin = 0x3E8000, length = 0x002000     /* on-chip FLASH */
	FLASHG      : origin = 0x3EA000, length = 0x002000     /* on-chip FLASH */
	FLASHF      : origin = 0x3EC000, length = 0x002000     /* on-chip FLASH */
	FLASHE      : origin = 0x3EE000, length = 0x002000     /* on-chip FLASH */
	FLASHD      : origin = 0x3F0000, length = 0x002000     /* on-chip FLASH */
	FLASHC      : origin = 0x3F2000, length = 0x002000     /* on-chip FLASH */
	FLASHA      : origin = 0x3F6000, length = 0x001F80     /* on-chip FLASH */
	CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
	BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
	CSM_PWL     : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */

	IQTABLES    : origin = 0x3FE000, length = 0x000B50     /* IQ Math Tables in Boot ROM */
	IQTABLES2   : origin = 0x3FEB50, length = 0x00008C     /* IQ Math Tables in Boot ROM */
	IQTABLES3   : origin = 0x3FEBDC, length = 0x0000AA     /* IQ Math Tables in Boot ROM */

	BOOTROM     : origin = 0x3FF27C, length = 0x000D44     /* Boot ROM */
	RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
	VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */

PAGE 1 : 
	RAML0	    : origin = 0x008000, length = 0x000800 /* on-chip RAM (L0-L1)*/
	BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
	RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
   	RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
   	dataRAM		: origin = 0x008800, length = 0x000400	   /* on-chip RAM block L1 */
   /*	CLAdataRAM		: origin = 0x008A00, length = 0x000200	   /* on-chip RAM block L1 */
   	RAML2		: origin = 0x008C00, length = 0x000400	   /* on-chip RAM block L2 */
	
	FLASHB      : origin = 0x3F4000, length = 0x002000     /* on-chip FLASH */

	CLA_CPU_MSGRAM  : origin = 0x001480, length = 0x000080 /* CLA-R/W, CPU-R message RAM */
	CPU_CLA_MSGRAM  : origin = 0x001500, length = 0x000080 /* CPU-R/W, CLA-R message RAM */
}
 
 
SECTIONS
{
   /* Allocate program areas: */
   .cinit            : > FLASHA | FLASHF,     PAGE = 0
   .pinit            : > FLASHA,     PAGE = 0
   .text             : > FLASHA,     PAGE = 0

   codestart         : > BEGIN       PAGE = 0
   
   ramfuncs          : LOAD = FLASHD, 
                       RUN = RAML3, 
                       LOAD_START(_RamfuncsLoadStart),
                       LOAD_END(_RamfuncsLoadEnd),
                       RUN_START(_RamfuncsRunStart),
                       PAGE = 0
                       

   	Cla1Prog         : LOAD = FLASHC, /* Note for running from RAM the load and RUN can be the same */
                      RUN = RAML3,
                      LOAD_START(_Cla1funcsLoadStart),
                       LOAD_SIZE(_Cla1funcsLoadSize),
                      LOAD_END(_Cla1funcsLoadEnd),
                      RUN_START(_Cla1funcsRunStart),
                      PAGE = 0
	
   Cla1Data		   : > dataRAM,		  PAGE = 1

   csmpasswds        : > CSM_PWL     PAGE = 0
   csm_rsvd          : > CSM_RSVD    PAGE = 0
   
   /* Allocate uninitalized data sections: */
   .stack            : > RAMM0,      PAGE = 1
//   .ebss             : > RAML0,    	 PAGE = 1
// Dto zostalo dodane, bo po dodaniu nowych funkcji (sine, pll, pid) nie wystarczlao pamieci na globalne itp
   .ebss             : >> RAML0 | RAML2 ,    	 PAGE = 1
   .esysmem          : > RAMM1,      PAGE = 1
	
   /* Initalized sections go in Flash */
   /* For SDFlash to program these, they must be allocated to page 0 */
   .econst           : > FLASHA      PAGE = 0
   .switch           : > FLASHA      PAGE = 0      

   /* Allocate IQ math areas: */
   //IQmath            : > FLASHA      PAGE = 0                  /* Math Code */
   // zabraklo miejsca
   IQmath            : > FLASHA | FLASHG     PAGE = 0                  /* Math Code */
   IQmathTables      : > IQTABLES     PAGE = 0, TYPE = NOLOAD   /* Math Tables In ROM */

   .bss_cla		       : > dataRAM,   PAGE = 1
   .scratchpad		       : > dataRAM,   PAGE = 1
   .const_cla       :  LOAD = FLASHE,
                       RUN = dataRAM,
                       RUN_START(_Cla1ConstRunStart),
                       LOAD_START(_Cla1ConstLoadStart),
                       LOAD_SIZE(_Cla1ConstLoadSize),
                       PAGE = 1

   Cla1ToCpuMsgRAM   : > CLA_CPU_MSGRAM PAGE = 1
   CpuToCla1MsgRAM   : > CPU_CLA_MSGRAM PAGE = 1
   ClaDataRam0		: > dataRAM,		  PAGE = 1

   .reset            : > RESET,      PAGE = 0, TYPE = DSECT
   vectors           : > VECTORS     PAGE = 0, TYPE = DSECT

	DLOG	 			: >	dataRAM,    PAGE = 1
   
   	SINTBL			: > FLASHB, 	PAGE = 1

 /* Uncomment the section below if calling the IQNexp() or IQexp()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)

   }
   */
   /* Uncomment the section below if calling the IQNasin() or IQasin()
      functions from the IQMath.lib library in order to utilize the
      relevant IQ Math table in Boot ROM (This saves space and Boot ROM
      is 1 wait-state). If this section is not uncommented, IQmathTables2
      will be loaded into other memory (SARAM, Flash, etc.) and will take
      up space, but 0 wait-state is possible.
   */
   /*
   IQmathTables3    : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
   {

              IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)

   }
   */

}
    

SECTIONS
{
	/*************       DPLIB Sections C28x      ************************/
	/* ADCDRV_1ch section */
	ADCDRV_1ch_Section				: > dataRAM				PAGE = 1
	
	/* ADCDRV_4ch section */
	ADCDRV_4ch_Section				: > dataRAM				PAGE = 1

	/* CNTL_2P2Z section */
	CNTL_2P2Z_Section				: > dataRAM				PAGE = 1
	CNTL_2P2Z_InternalData			: > dataRAM				PAGE = 1
	CNTL_2P2Z_Coef					: > dataRAM				PAGE = 1
	
	/* CNTL_3P3Z section */
	CNTL_3P3Z_Section				: > dataRAM				PAGE = 1
	CNTL_3P3Z_InternalData			: > dataRAM				PAGE = 1
	CNTL_3P3Z_Coef					: > dataRAM				PAGE = 1
	
	
	/*DLOG_4CH section */
	DLOG_4CH_Section				: > dataRAM				PAGE = 1
	DLOG_BUFF						: > dataRAM				PAGE = 1
	
	/*MATH_EMAVG section */
	MATH_EMAVG_Section				: > dataRAM				PAGE = 1
	
	/*PFC_ICMD section */
	PFC_ICMD_Section				: > dataRAM				PAGE = 1
	
	/*PFC_INVSQR section */
	PFC_INVSQR_Section				: > dataRAM				PAGE = 1
	
	/* PWMDRV_1ch driver section */
	PWMDRV_1ch_Section				: > dataRAM				PAGE = 1
	
	/* PWMDRV_1chHiRes driver section */
	PWMDRV_1chHiRes_Section			: > dataRAM				PAGE = 1
	
	/* PWMDRV_PFC2PhiL driver section */
	PWMDRV_PFC2PhiL_Section			: > dataRAM				PAGE = 1
	
 	/* PWMDRV_PSFB driver section */
	PWMDRV_PSFB_Section				: > dataRAM				PAGE = 1
	
	/* PWMDRV_DualUpDwnCnt driver section */
	PWMDRV_DualUpDwnCnt_Section		: > dataRAM				PAGE = 1
	
	/* PWMDRV_ComplPairDB driver section */
	PWMDRV_ComplPairDB_Section		: > dataRAM				PAGE = 1
	
	/* PWMDRV_1ch_UpDwnCntCompl driver section */
	PWMDRV_1ch_UpDwnCntCompl_Section	: > dataRAM				PAGE = 1
	
	/* ZeroNet_Section  */
	ZeroNet_Section					: > dataRAM				PAGE = 1
	
	/*************       DPLIB Sections CLA      ************************/
	/* ADCDRV_1ch_CLA section */	
	ADCDRV_1ch_CLA_Section    		: > CPU_CLA_MSGRAM 	PAGE = 1
	
	/* ADCDRV_4ch_CLA section */	
	ADCDRV_4ch_CLA_Section    		: > CPU_CLA_MSGRAM 	PAGE = 1
	
	/* CNTL_2P2Z_CLA controller sections */
	CNTL_2P2Z_CLA_Section     		: > CPU_CLA_MSGRAM 		PAGE = 1  
	CNTL_2P2Z_CLA_InternalData 	    : > CLA_CPU_MSGRAM  	PAGE = 1
	CNTL_2P2Z_CLA_Coef				: >	CPU_CLA_MSGRAM		PAGE = 1
	
	/* CNTL_3P3Z_CLA controller sections */
	CNTL_3P3Z_CLA_Section     		: > CPU_CLA_MSGRAM 		PAGE = 1  
	CNTL_3P3Z_CLA_InternalData 	    : > CLA_CPU_MSGRAM  	PAGE = 1
	CNTL_3P3Z_CLA_Coef				: >	CPU_CLA_MSGRAM		PAGE = 1
	
	/*MATH_EMAVG_CLA sections */
	MATH_EMAVG_CLA_Section			: > CPU_CLA_MSGRAM		PAGE = 1
	MATH_EMAVG_CLA_InternalData		: > CPU_CLA_MSGRAM		PAGE = 1

	/*PFC_ICMD_CLA sections*/
	PFC_ICMD_CLA_Section			: > CPU_CLA_MSGRAM		PAGE = 1
	PFC_ICMD_CLA_InternalData		: > CPU_CLA_MSGRAM		PAGE = 1
	
	/*PFC_INVSQR_CLA sections*/
	PFC_INVSQR_CLA_Section			: > CPU_CLA_MSGRAM		PAGE = 1
	PFC_INVSQR_CLA_InternalData		: > CPU_CLA_MSGRAM		PAGE = 1
	
	/* PWMDRV_1ch_CLA driver section */
	PWMDRV_1ch_CLA_Section    		: > CPU_CLA_MSGRAM 	PAGE = 1

	/* PWMDRV_1chHiRes_CLA driver section */
	PWMDRV_1chHiRes_CLA_Section		: > CPU_CLA_MSGRAM 	PAGE = 1
	
 	/* PWMDRV_PFC2PhiL driver section */
	PWMDRV_PFC2PhiL_CLA_Section		: > CPU_CLA_MSGRAM 	PAGE = 1
	
 	/* PWMDRV_PSFB_CLA driver section */
	PWMDRV_PSFB_CLA_Section	 		: > CPU_CLA_MSGRAM 	PAGE = 1

	/* PWMDRV_DualUpDwnCnt_CLA driver section */
	PWMDRV_DualUpDwnCnt_CLA_Section	 : > CPU_CLA_MSGRAM		PAGE = 1
	
	/* PWMDRV_ComplPairDB_CLA driver section */
	PWMDRV_ComplPairDB_CLA_Section	 : > CPU_CLA_MSGRAM		PAGE = 1
	
	/* ZeroNetCLA_Section  */
	ZeroNetCLA_Section				 : > CPU_CLA_MSGRAM 	PAGE = 1


}

 

But after these changes no register changes are made.