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TMS320F280048C-Q1: Query

Shinu.V.Mathew
Expert 7445 points
Part Number: TMS320F280048C-Q1
Other Parts Discussed in Thread: C2000WARE

Hi Team,

My customer is evaluating F280049C Launchpad for one the applications and need to use peripherals like SPI-A, SPI-B, SCI-A, SCI-B etc along with some preprocessing and control loops. The execution periodicity is 10us which they are generating through CPUTimer0 interrupt. What is the easiest way to schedule different activities ? For eg, they need to use a GPIO to function as ChipSelect of SPI-A, another for SPI-B, 3rd one for SCI-A Transmit/Receive enable etc.

Not able to use the dedicated CS of these peripherals due to some other reasons. Customer want to enable SPI-A CS through GPIO at one point of time, start transmitting the data and disable the CS after transmitting data. They are not able to use delay functions in between since they need CPU cycles for other preprocessing functions. 

Can you please help with your comments to address this issue. 

Regards, Shinu. 

  • 0
    TI__Guru 55700 points

    Shinu,

    For SPI communication, you can use DMA to initiate SPI transmit / receiver. Please check spi_ex3_loopback_dma example available in C2000Ware

    Path: <C2000Ware>\driverlib\f28004x\examples\spi

    You use CPU timer to initiate DMA.

    For SCI, instead of polling method use interrupt method. This way you can avoid wasting CPU cycle polling and using delay function.

    Regards,

    Manoj

  • 0 in reply to Manoj Santha Mohan
    Intellectual 840 points

    Hi Manoj,

       Thanks for the reply. I was mentioning about scheduling the enable signals of peripherals (eg :- Chip select of SPI, Transmit/Receive enable pin of UART Transceiver etc). One way to do it is set a GPIO, transmit the data by assigning to transmit buffer, wait for 'x' amount of time, clear the GPIO. I used to do the same by introducing other operations (whose execution time equals the data transmission time, 'x' amount of time) after transmit buffer loading and then clear the GPIO. I need a more elegant solution to it. The amount of data to transmit or receive is less, so DMA is not required I think.

    Regards

       Karthik R

  • 0 in reply to Karthik Raveendranath
    TI__Guru 55700 points

    Karthik,

    One way to do it is set a GPIO, transmit the data by assigning to transmit buffer, wait for 'x' amount of time, clear the GPIO. I used to do the same by introducing other operations (whose execution time equals the data transmission time, 'x' amount of time) after transmit buffer loading and then clear the GPIO. I need a more elegant solution to it.

    Below method uses both SPITXFIFO / SPIRXFIFO ISR routines to transmit and receive and uses CPU timer ISR to initiate SPI write / read transaction. You can use similar method for SCI as well.

    1) In SPI initialization, make sure you don't enable FIFO RX / TX interrupt.

    2) Inside CPU Timer ISR:

    • FIFOlevel (global variable) = number of bits to be transmitted (or) received
    • If SPI Write: Make sure TXbuffer is filled with data to be transmitted
    • If SPI Read: Make sure TXbuffer is filled with dummy data to be transmitted for receive operation
    • Bring chip select pin (GPIO low)
    • Set FIFO RX / TX level as shown below and enable RX / TX FIFO interrupt

        FIFOlevel = SPI_FIFO_RX2;
        SPI_clearInterruptStatus(SPIA_BASE, SPI_INT_RXFF | SPI_INT_TXFF);
        SPI_setFIFOInterruptLevel(SPIA_BASE, SPI_FIFO_TXEMPTY, FIFOlevel);
        SPI_enableInterrupt(SPIA_BASE, SPI_INT_RXFF | SPI_INT_TXFF);

    3) Configure your SPI TX FIFO ISR as shown below

    • SPI TX FIFO gets triggered because SPI TX FIFO is empty
    • Disable SPI TX FIFO interrupt avoid more SPI TX FIFO interrupts within one SPI transaction
    • Write to SPITXBUF as shown below
    • Clear the flag and acknowledge interrupt

    __interrupt void spiTxFIFOISR(void)
    {
        uint16_t i;

        SPI_disableInterrupt(SPIA_BASE, SPI_INT_TXFF);
        //
        // Send data
        //
        for(i = 0; i < FIFOlevel; i++)
        {
           SPI_writeDataNonBlocking(SPIA_BASE, sData[i]);
        }

         //
        // Clear interrupt flag and issue ACK
        //
        SPI_clearInterruptStatus(SPIA_BASE, SPI_INT_TXFF);

        Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP6);
    }

    4) Configure your SPI RX FIFO ISR as shown below

    • SPI RX FIFO gets triggered because SPI RX FIFO is filled with FIFOlevel
    • Disable SPI RX FIFO interrupt avoid more SPI RX FIFO interrupts within one SPI transaction
    • Read SPIRXBUF as shown below
    • Clear the flag and acknowledge interrupt
    • Pull chip select (GPIO) high

     __interrupt void spiRxFIFOISR(void)
    {
        uint16_t i;
        SPI_disableInterrupt(SPIA_BASE, SPI_INT_RXFF);
        //
        // Read data
        //
        for(i = 0; i < FIFOlevel; i++)
        {
            rData[i] = SPI_readDataNonBlocking(SPIA_BASE);
        }

        //
        // Clear interrupt flag and issue ACK
        //
        SPI_clearInterruptStatus(SPIA_BASE, SPI_INT_RXFF);

        Interrupt_clearACKGroup(INTERRUPT_ACK_GROUP6);

        GPIO_writePin(19, 1);
    }

    Regards,

    Manoj