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TIDM-1007: CPU usage measurements

Part Number: TIDM-1007
Other Parts Discussed in Thread: POWERSUITE, , TIDM-02008, SFRA

Dear all,

in the process of trying to implement 3 current loops instead of just one, I've performed measurements on CPU usage, just to make sure there is enough time to do it with C28x.

The software setup is based on the LAB3 example : current + voltage loops, in AC/DC mode (without CLA). I've experimented two methods:

- write the fonction GPIO_writePin() in the control loop to measure a pulse width on the selected pin.
- tick the option Run>Clock>Enable and measure how many cycles the control loop takes.

With both methods, I've found that the ISR1 interrupt takes approximately 6µs (out of a 10µs interrupt period) without adaptative dead time and phase shedding. So, the ISR1 interrupt takes about 60% of the CPU, and about 75% with advanced options.

However, the numbers stated in the following post are quite different : 43% CPU usage - up to 60% CPU usage with advanced options.
Please note that the TIDM-1007/TIDM-2008 code has been otherwise left unchanged, as provided in C2000 powerSUITE.

Can you please help me determine the possible causes of such differences ?

Any help will be appreciated, thanks.

  • Hi,

    We added CPU utilization in the latest user guide. Please check the link below. TIDM-02008 is the new reference design number to highlight the bi-directional power flow. In the worst case scenario, ISR1 takes 53% CPU budget.

    There are several factors that impact the CPU utilization. To get the best result, we disabled several functions that are not practically needed for PFC operation such as 

    1. Individual current sensing

    2. Data logger

    3. SFRA

    Also, as mentioned in user guide, SPLL method (Notch SPLL gives the best number) and the optimization level also affect CPU utilization.