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F28M36P63C2: F28M36P63C2: IO lines operating not operating as expected

Part Number: F28M36P63C2

Hi,

I am trying to read the logic low condition on an external peripheral using F28M36P63C2's GPIO12,13 and 14. There are no decaps on these pins but I am using an external 5K pull up with a 1500 pF filter cap on all these lines. On the scope, I am seeing a ~220KHz noise on these lines, which is very hard to filter. When I connect an oscilloscope probe, especially a differential probe having a 250KOhm input impedance (my circuit is floating in respect to earth ground) , the probe loads the circuit and the target line drops close to logic low. I am seeing this issue on multiple boards where the firmware falsely detects these pins as a logic low. The target peripheral pins have a sink current of 3mA. 

I am wondering whether I am driving these pins properly, what is the minimum current that needs to sink to these pins for a robust drive strength . Why are these pins so much susceptible to the noise. What steps can I take to improve the noise immunity of these lines and filter this noise .

Thanks 

  • Jagbir,

    based on the other question you have referenced I think its safe to assume that you are already using the GPIO input qualifier.

    Though centered around another device I happen to like the way this post describes the input qualifier. https://e2e.ti.com/blogs_/b/industrial_strength/archive/2018/05/22/qualification-on-a-noisy-input-signal 

    Please note that if the signal is oscillating at the perfect frequency it may alias with the input qualifiers frequency and still transition low/high.

    Dumb question, but how do you know the 220kHz signal is there if you cant see it on a scope?

    Jagbir Singh said:
    I am wondering whether I am driving these pins properly, what is the minimum current that needs to sink to these pins for a robust drive strength

    I typically think of this as VIL. Or the voltage required to reach a low-level input. However the amount of current required to pull a pin low is specified as IIL. Both of these values can be found in the Datasheet under "Electrical Characteristics": https://www.ti.com/lit/gpn/f28m36p63c2 

    Additionally, any GPIO is susceptible to noise, if the voltage is swinging up and down it can be read. I think its better to try and figure out where the noise is coming from and then try to address why it is being coupled to these signals in particular.

    Regards,
    Cody 

  • I can see the 220 KHz noise signal on the scope on these GPIO lines. This noise is also on the 3.3, 1.8 and 1.2 supply pins. Additionally, oscilloscope probes with less than 1 Mega Ohm input impedance, tend to load the GPIO lines during measurements. An external pull 5K pull up and 1500pf filter cap helps a bit with the noise but it doesn't remove the noise completely. The questions is why these particular GPIO pins are so susceptible to noise, even to O-scope probes attachments. Will a stronger pull up say 2k,combined with decap near GPIO will help the cause. The GPIO 7-9 drive a 50KHz PWM, since these are on the same channel/die do you think there is a chance of ground bounce, Vcc bounce type of noise.

  • Jagbir,

    the device doesn't have any internal weakness making these pins susceptible to noise that I know of.

    Noise of this type is often a board layout issue so I recommend looking at how these traces are routed, and the quality of the ground reference near where they are routed. The longer the ground return path the more susceptible they will be to noise. I cannot comment on if this issue is specifically ground bounce, but it could be being how many places you are seeing the noise.

    Just thinking through how the 1500pF cap is helping... well I assume its making a Low pass filter with the few ohms of resistance in the PCB trace. That of course would mean that the cutoff frequency would be much much higher than 220kHz and not making a huge impact.

    Regards,
    Cody 

  • What's the minimum pull up value for these GPIO's. Can we go lower than 2.2 K.

  • Jagbir,

    as long as these pins are used as inputs there is no limit on how large of a pull up you can you. Please note unless your driver is an open drain i see very little chance of this helping your signal quality.

    If the pin is used as an output then you must ensure that the current limits are not violated as specified in the datasheet. Please note that using a stronger pull resistor may effect the slew rate and ultimately the Vout that the GPIO can achieve.

    Regards,
    Cody

  • I am configuring these GPIOs as input. These GPIOs are connected to the drain of the the open drain driver. How can I calculate the slew rate with different pull up values.

  • Jagbir,

    that would depend on your driving device. I would suggest you look at it's Datasheet.

    Regards,
    Cody 

  • I am monitoring for the driver pin(MAX14890E) to go low but the driver has Output Low Voltage (Vol ) level as 0.4V . As you know Vol for  F28M36P  is 1.1V at 3V3 supply. How do I lower the logic threshold for the MCU so that it does not falsely detect the driver's logic low.

  • Jagbir,

    Vol is typically specified as the maximum voltage that could be output for a logic low level. Your driver pin spec tells you to expect a value less than 0.4V.

    While the driver's Vol does matter in this case the F28M36P's Vol does not . Vol is only a spec indicating the output level for a logic low, you are not using these pins as an output so that is irrelevant for F28M36P. Please look at Vil, which is VDDIO*0.3 . This means you can have any voltage below 0.99V and it will look like a 0 to the device.

    Since your driver's spec is smaller than the input pins spec for F28M36P, you should be OK. Please also note that for F28M36P VIL and VOL are device characteristics and are not programmable or adjustable.

    Regards,
    Cody 

  • I am seeing noise transients on the VDDIO3V3,VDDIO1V8 and VDDIO1V2 pins when the load is turned on. How this VDDIO noise can adversely impact these GPIO measurements.

  • Jagbir,

    The datasheet specifies the min and maximum operating voltage, it appears your noise is outside of these ranges. If you leave the recommended operating conditions we cannot guarantee the other specifications listed in the datasheet. Particularly in this case device lifetime and sensitive peripherals could be affected. 

    I personally expect that GPIO's to be much more robust to this kind of noise compared to say HRPWM or Analog circuits, but nevertheless this issue should be addressed.

    You should review your PCB layout.

    1. Do you have decoupling caps near the device?
    2. Where is this noise being picked up?
    3. Are there any 500kHz signals that could be being coupled?
      1. How are these signals separated from the power planes?
      2. Ground planes?
    4. Is the ground return path short and clean?

    Assuming you feel this PCB design is good and not marginal, then you could investigate issues with this particular board.

    1. Can you probe another PCB assembly, is this Power rail noise visible?
    2. Have you confirmed that the solder connections are good using x-ray? Perhaps this F28M36 unit has some missing or marginal ground solder connections.
    3. Preform an A/B swap with a known good F28M36 then this could indicate if this device is at fault or not. If the issue remains then it is very likely an assembly issue or other inherit design susceptibility, but please know that issues like number 2 above could also be fixed by preforming an A/B swap.

    Regards,
    Cody