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LAUNCHXL-F28027F: Can't boot program from flash.

Part Number: LAUNCHXL-F28027F
Other Parts Discussed in Thread: C2000WARE, TMS320F280025C, TMS320F280049C

Hello!

I can't boot any program from flash using LAUNCH-XLF28027F. I am using driverlib examples from C2000Ware and even LaunchPadDemo doesn't work. I mean I can load program using Flash configuration but after power ON the program doesn't start. I tried to switch S1 to ON-ON-OFF position and still no result. How can I handle this issue?

BR,

Dawid.

  • Hello,

    Is this a new board?  Is it possible that someone previously programmed the "GetMode" option to be something other than flash?  Please refer to the Technical Reference Manual - section "Bootloader Modes" the table "OTP Values for GetMode" for more information.  

    If GetMode is programmed, then you can program additional bits to make the OTP_KEY invalid.  This will revert back to boot to flash.  Unfortunately you cannot erase the OTP.

    If this is not an existing design, I would also suggest considering one of our newer devices instead - such as the TMS320F280049C or TMS320F280025C family. We have made a lot of improvements over the years. 

    Best Regards

    Lori 

  • Yes, this is new board and I didn't change anything in those registers. How cain I check GetMode?

  • Dawid,

    The documentation I referenced has the memory location where the get mode values are located.  You can observe these in Code Composer Studio.  On a fresh device they should all be 0xFFFF  (erased). 

    Regards

    Lori

  • I am not sure if I did it in a correct way but here it is:

    Values in watched expressions seem ok.

  • Dawid,

    Yes, it looks correct.

    I should have asked - are you using a project that has been built for flash?

    This application note guides through what is involved in running a program from flash vs RAM www.ti.com/lit/spra958

    Regards,

    Lori

  • I based my project on typical project from creator:

    and I am using release build option. To be honest I thought it is prepared for flashing.

    Even it isn't raw LaunchPadDemo imported from Resource Explorer looks like this:

    and I can't boot it from flash either.

    Here is memory allocation diagram:

    and *.cmd file:

    0508.TMS320F28027.txt
    /*
     * Copyright (c) 2015-2020, Texas Instruments Incorporated
     * All rights reserved.
     *
     * Redistribution and use in source and binary forms, with or without
     * modification, are permitted provided that the following conditions
     * are met:
     *
     * *  Redistributions of source code must retain the above copyright
     *    notice, this list of conditions and the following disclaimer.
     *
     * *  Redistributions in binary form must reproduce the above copyright
     *    notice, this list of conditions and the following disclaimer in the
     *    documentation and/or other materials provided with the distribution.
     *
     * *  Neither the name of Texas Instruments Incorporated nor the names of
     *    its contributors may be used to endorse or promote products derived
     *    from this software without specific prior written permission.
     *
     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     */
    /*
     *  ======== TMS320F28027.cmd ========
     *  Define the memory block start/length for the F28027
     */
    
    /*
     *  PAGE 0 will be used to organize program sections
     *  PAGE 1 will be used to organize data sections
     *
     *  Notes:
     *        Memory blocks on F2802x are uniform (ie same
     *        physical memory) in both PAGE 0 and PAGE 1.
     *        That is the same memory region should not be
     *        defined for both PAGE 0 and PAGE 1.
     *        Doing so will result in corruption of program
     *        and/or data.
     *
     *        L0 memory blocks are mirrored - that is
     *        they can be accessed in high memory or low memory.
     *        For simplicity only one instance is used in this
     *        linker file.
     */
    
    MEMORY
    {
    PAGE 0:    /* Program Memory */
    
        OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */
        FLASH       : origin = 0x3F0000, length = 0x007F80     /* on-chip FLASH */
        CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Program with all 0x0000 when CSM is in use. */
        BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Used for "boot to Flash" bootloader mode. */
        CSM_PWL     : origin = 0x3F7FF8, length = 0x000008     /* CSM password locations in FLASH */
    
        IQTABLES    : origin = 0x3FE000, length = 0x000B50     /* IQ Math Tables in Boot ROM */
        IQTABLES2   : origin = 0x3FEB50, length = 0x00008C     /* IQ Math Tables in Boot ROM */
        IQTABLES3   : origin = 0x3FEBDC, length = 0x0000AA	   /* IQ Math Tables in Boot ROM */
    
        ROM         : origin = 0x3FF27C, length = 0x000D44     /* Boot ROM */
        RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
        VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */
    
    PAGE 1 :   /* Data Memory */
    
        M01SARAM    : origin = 0x000000, length = 0x000800     /* on-chip RAM block M0, M1 */
        PIEVECT     : origin = 0xD00,    length = 0x100
        L0SARAM     : origin = 0x008000, length = 0x001000     /* on-chip RAM block L0 */
    }
    
    /*
     *  Allocate sections to memory blocks.
     *  Note:
     *      codestart   user defined section in DSP28_CodeStartBranch.asm
     *                  used to redirect code execution when booting to flash
     *
     *      ramfuncs    user defined section to store functions that will be
     *                  copied from Flash into RAM
     */
    
    SECTIONS
    {
        /* Allocate program areas: */
        .cinit              : > FLASH       PAGE = 0
        .pinit              : > FLASH       PAGE = 0
        .text               : > FLASH       PAGE = 0
        codestart           : > BEGIN       PAGE = 0
        ramfuncs            : LOAD = FLASH      PAGE = 0,
                              RUN  = L0SARAM    PAGE = 1,
                              LOAD_START(_RamfuncsLoadStart),
                              LOAD_SIZE(_RamfuncsLoadSize),
                              LOAD_END(_RamfuncsLoadEnd),
                              RUN_START(_RamfuncsRunStart)
    
        csmpasswds          : > CSM_PWL     PAGE = 0
        csm_rsvd            : > CSM_RSVD    PAGE = 0
    
        /* Allocate uninitalized data sections: */
        .stack              : > M01SARAM | L0SARAM      PAGE = 1
        .ebss               : >> M01SARAM | L0SARAM      PAGE = 1
        .data               : > M01SARAM | L0SARAM      PAGE = 1
        .esysmem            : > L0SARAM | M01SARAM      PAGE = 1
        .cio                : > L0SARAM | M01SARAM      PAGE = 1
    
        /* Initalized sections go in Flash */
        /* For SDFlash to program these, they must be allocated to page 0 */
        .econst             : > FLASH       PAGE = 0
        .switch             : > FLASH       PAGE = 0
        .args               : > FLASH       PAGE = 0
    
    #ifdef __TI_COMPILER_VERSION__
    #if __TI_COMPILER_VERSION__ >= 15009000
        .TI.ramfunc         : {} LOAD = FLASH    PAGE = 0,
                                 RUN  = L0SARAM  PAGE = 1,
                                 table(BINIT)
    #endif
    #endif
    
        /* Allocate IQ math areas: */
        IQmath              : > FLASH       PAGE = 0            /* Math Code */
        IQmathTables        : > IQTABLES    PAGE = 0, TYPE = NOLOAD
    
        /*
         *  Uncomment the section below if calling the IQNexp() or IQexp()
         *  functions from the IQMath.lib library in order to utilize the
         *  relevant IQ Math table in Boot ROM (This saves space and Boot ROM
         *  is 1 wait-state). If this section is not uncommented, IQmathTables2
         *  will be loaded into other memory (SARAM, Flash, etc.) and will take
         *  up space, but 0 wait-state is possible.
         */
        /*
        IQmathTables2       : > IQTABLES2   PAGE = 0, TYPE = NOLOAD
        {
            IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
        }
        */
    
        /*
         *  Uncomment the section below if calling the IQNasin() or IQasin()
         *  functions from the IQMath.lib library in order to utilize the
         *  relevant IQ Math table in Boot ROM (This saves space and Boot ROM
         *  is 1 wait-state). If this section is not uncommented, IQmathTables2
         *  will be loaded into other memory (SARAM, Flash, etc.) and will take
         *  up space, but 0 wait-state is possible.
         */
        /*
        IQmathTables3       : > IQTABLES3   PAGE = 0, TYPE = NOLOAD
        {
            IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
        }
        */
    }
    

    If this set is not correct maybe anyone has sample cmd file for flash applications?

  • I would be skeptical of the "release" build has all of the hooks needed.  The hooks are described in the application note I mentioned. 

    It does look like the LP example has flash support. 

    The key bits in the linker command file is the memory BEGIN - which looks like it is in the right place.  And then the branch to BEGIN which is the section codestart.  That also looks ok in the linker command file.

    I'm not sure what the issue is.  Try debugging the problem with Code Composer Studio (CCS) attached.   

    • Flash the device
    • Power-reset to make sure only flash is populated
    • Conncect CCS and in CCS load symbols only.
    • See if the boot ROM exits to the BEGIN memory location and if that branches to your _cinit code. 

    To get started, you may find this workshop helpful: https://training.ti.com/c2000-f28004x-microcontroller-workshop?context=1137755-1139641-1137780

    Unfortunately the material is bit dated as far as the CCS version.  But the concepts still apply.

    Here are a number of FAQs for this flash, including running from flash 

    https://e2e.ti.com/support/microcontrollers/c2000/f/c2000-microcontrollers-forum/757585/faq-f05-flash-frequently-asked-questions

    https://e2e.ti.com/support/microcontrollers/c2000/f/c2000-microcontrollers-forum/758797/faq-f05-flash-how-do-i-convert-a-ram-based-project-to-a-flash-based-project

    Regards

    Lori

  • Finally, I handled with correct *.cmd files. I attach them here for another Users:

    F2802x_generic_flash_txt.txt
    /*
    //###########################################################################
    //
    // FILE:    F2802x_generic_flash.cmd
    //
    // TITLE:   Generic Linker Command File for f2802x devices
    //
    //###########################################################################
    // $TI Release: F2802x Support Library v230 $
    // $Release Date: Fri May  8 07:43:05 CDT 2015 $
    // $Copyright: Copyright (C) 2008-2015 Texas Instruments Incorporated -
    //             http://www.ti.com/ ALL RIGHTS RESERVED $
    //###########################################################################
    */
    
    /* ======================================================
    // For Code Composer Studio V2.2 and later
    // ---------------------------------------
    // In addition to this memory linker command file,
    // add the header linker command file directly to the project.
    // The header linker command file is required to link the
    // peripheral structures to the proper locations within
    // the memory map.
    //
    // The header linker files are found in <base>\f2802x_Headers\cmd
    //
    // For BIOS applications add:      F2802x_Headers_BIOS.cmd
    // For nonBIOS applications add:   F2802x_Headers_nonBIOS.cmd
    ========================================================= */
    
    /* ======================================================
    // For Code Composer Studio prior to V2.2
    // --------------------------------------
    // 1) Use one of the following -l statements to include the
    // header linker command file in the project. The header linker
    // file is required to link the peripheral structures to the proper
    // locations within the memory map                                    */
    
    /* Uncomment this line to include file only for non-BIOS applications */
    /* -l F2802x_Headers_nonBIOS.cmd */
    
    /* Uncomment this line to include file only for BIOS applications */
    /* -l F2802x_Headers_BIOS.cmd */
    
    /* 2) In your project add the path to <base>\f2802x_headers\cmd to the
       library search path under project->build options, linker tab,
       library search path (-i).
    /*========================================================= */
    
    /* Define the memory block start/length for the F2802x
       PAGE 0 will be used to organize program sections
       PAGE 1 will be used to organize data sections
    
       Notes:
             Memory blocks on F2802x are uniform (ie same
             physical memory) in both PAGE 0 and PAGE 1.
             That is the same memory region should not be
             defined for both PAGE 0 and PAGE 1.
             Doing so will result in corruption of program
             and/or data.
    
             Contiguous SARAM memory blocks or flash sectors can be
             be combined if required to create a larger memory block.
    */
    
    MEMORY
    {
    PAGE 0:    /* Program Memory */
               /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
    
       RAMM0       : origin = 0x000050, length = 0x0003B0     /* on-chip RAM block M0 */
       OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */
       FLASHA      : origin = 0x3F7000, length = 0x000F80     /* on-chip FLASH */
       CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
       BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
       CSM_PWL_P0  : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */
       FLASHB      : origin = 0x3F6000, length = 0x001000     /* on-chip FLASH */
    
    
    
       IQTABLES    : origin = 0x3FE000, length = 0x000B50     /* IQ Math Tables in Boot ROM */
       IQTABLES2   : origin = 0x3FEB50, length = 0x00008C     /* IQ Math Tables in Boot ROM */
       IQTABLES3   : origin = 0x3FEBDC, length = 0x0000AA      /* IQ Math Tables in Boot ROM */
    
       ROM         : origin = 0x3FF27C, length = 0x000D44     /* Boot ROM */
       RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
       VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */
    
    PAGE 1 :   /* Data Memory */
               /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
               /* Registers remain on PAGE1                                                  */
    
       BOOT_RSVD   : origin = 0x000000, length = 0x000050     /* Part of M0, BOOT rom will use this for stack */
       RAMM1       : origin = 0x000400, length = 0x000400     /* on-chip RAM block M1 */
       RAML0       : origin = 0x008000, length = 0x000400     /* on-chip RAM block L0 */
    
    }
    
    /* Allocate sections to memory blocks.
       Note:
             codestart user defined section in DSP28_CodeStartBranch.asm used to redirect code
                       execution when booting to flash
             ramfuncs  user defined section to store functions that will be copied from Flash into RAM
    */
    
    SECTIONS
    {
    
       /* Allocate program areas: */
       codestart           : > BEGIN       PAGE = 0
    
       ramfuncs            : LOAD = FLASHA,
                             RUN = RAMM0,
                             LOAD_START(_RamfuncsLoadStart),
                             LOAD_SIZE(_RamfuncsLoadSize),
                             RUN_START(_RamfuncsRunStart),
                             PAGE = 0
    
       .cinit              : >  FLASHA | FLASHB,      PAGE = 0
       .pinit              : >  FLASHA | FLASHB,      PAGE = 0
       .text               : >> FLASHA | FLASHB,      PAGE = 0
    
       csmpasswds          : > CSM_PWL_P0,  PAGE = 0
       csm_rsvd            : > CSM_RSVD,    PAGE = 0
    
       /* Allocate uninitalized data sections: */
       .stack              : >  RAMM1,             PAGE = 1
       .ebss               : >> RAMM1 | RAML0,     PAGE = 1
       .esysmem            : >> RAMM1 | RAML0,     PAGE = 1
    
       /* Initalized sections go in Flash */
       /* For SDFlash to program these, they must be allocated to page 0 */
       .econst             : >> FLASHA | FLASHB,   PAGE = 0
       .switch             : >> FLASHA | FLASHB,   PAGE = 0
    
       /* Allocate IQ math areas: */
       IQmath              : >> FLASHA | FLASHB,   PAGE = 0            /* Math Code */
       IQmathTables        : >  IQTABLES,          PAGE = 0, TYPE = NOLOAD
    
       /* Uncomment the section below if calling the IQNexp() or IQexp()
          functions from the IQMath.lib library in order to utilize the
          relevant IQ Math table in Boot ROM (This saves space and Boot ROM
          is 1 wait-state). If this section is not uncommented, IQmathTables2
          will be loaded into other memory (SARAM, Flash, etc.) and will take
          up space, but 0 wait-state is possible.
       */
       /*
       IQmathTables2    : > IQTABLES2, PAGE = 0, TYPE = NOLOAD
       {
    
                  IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
    
       }
       */
       /* Uncomment the section below if calling the IQNasin() or IQasin()
          functions from the IQMath.lib library in order to utilize the
          relevant IQ Math table in Boot ROM (This saves space and Boot ROM
          is 1 wait-state). If this section is not uncommented, IQmathTables2
          will be loaded into other memory (SARAM, Flash, etc.) and will take
          up space, but 0 wait-state is possible.
       */
       /*
       IQmathTables3    : > IQTABLES3, PAGE = 0, TYPE = NOLOAD
       {
    
                  IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
    
       }
       */
    
       /* .reset is a standard section used by the compiler.  It contains the */
       /* the address of the start of _c_int00 for C Code.   /*
       /* When using the boot ROM this section and the CPU vector */
       /* table is not needed.  Thus the default type is set here to  */
       /* DSECT  */
       .reset              : > RESET,      PAGE = 0, TYPE = DSECT
       vectors             : > VECTORS     PAGE = 0, TYPE = DSECT
    
    }
    
    /*
    //===========================================================================
    // End of file.
    //===========================================================================
    */
    
    

    F2802x_Headers_nonBIOS_txt.txt
    /*
    //###########################################################################
    //
    // FILE:    F2802x_Headers_nonBIOS.cmd
    //
    // TITLE:   F2802x Peripheral registers linker command file 
    //
    // DESCRIPTION: 
    // 
    //          This file is for use in Non-BIOS applications.
    //
    //          Linker command file to place the peripheral structures 
    //          used within the F2802x headerfiles into the correct memory
    //          mapped locations.
    //
    //          This version of the file includes the PieVectorTable structure.
    //          For BIOS applications, please use the F2802x_Headers_BIOS.cmd file
    //          which does not include the PieVectorTable structure.
    //
    //###########################################################################
    // $TI Release: F2802x Support Library v230 $
    // $Release Date: Fri May  8 07:43:05 CDT 2015 $
    // $Copyright: Copyright (C) 2008-2015 Texas Instruments Incorporated -
    //             http://www.ti.com/ ALL RIGHTS RESERVED $
    //###########################################################################
    */
    
    MEMORY
    {
     PAGE 0:    /* Program Memory */
    
     PAGE 1:    /* Data Memory */
     
       DEV_EMU     : origin = 0x000880, length = 0x000105     /* device emulation registers */
         SYS_PWR_CTL : origin = 0x000985, length = 0x000003     /* System power control registers */
       FLASH_REGS  : origin = 0x000A80, length = 0x000060     /* FLASH registers */
       CSM         : origin = 0x000AE0, length = 0x000010     /* code security module registers */
       
       ADC_RESULT  : origin = 0x000B00, length = 0x000020     /* ADC Results register */
       
       CPU_TIMER0  : origin = 0x000C00, length = 0x000008     /* CPU Timer0 registers */
       CPU_TIMER1  : origin = 0x000C08, length = 0x000008     /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
       CPU_TIMER2  : origin = 0x000C10, length = 0x000008     /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
    
       PIE_CTRL    : origin = 0x000CE0, length = 0x000020     /* PIE control registers */
       PIE_VECT    : origin = 0x000D00, length = 0x000100     /* PIE Vector Table */
    
       COMP1       : origin = 0x006400, length = 0x000020     /* Comparator 1 registers */
       COMP2       : origin = 0x006420, length = 0x000020     /* Comparator 2 registers */
       
       EPWM1       : origin = 0x006800, length = 0x000040     /* Enhanced PWM 1 registers */
       EPWM2       : origin = 0x006840, length = 0x000040     /* Enhanced PWM 2 registers */
       EPWM3       : origin = 0x006880, length = 0x000040     /* Enhanced PWM 3 registers */
       EPWM4       : origin = 0x0068C0, length = 0x000040     /* Enhanced PWM 4 registers */
    
       ECAP1       : origin = 0x006A00, length = 0x000020     /* Enhanced Capture 1 registers */
     
       GPIOCTRL    : origin = 0x006F80, length = 0x000040     /* GPIO control registers */
       GPIODAT     : origin = 0x006FC0, length = 0x000020     /* GPIO data registers */
       GPIOINT     : origin = 0x006FE0, length = 0x000020     /* GPIO interrupt/LPM registers */
                     
       SYSTEM      : origin = 0x007010, length = 0x000020     /* System control registers */
       
       SPIA        : origin = 0x007040, length = 0x000010     /* SPI-A registers */
       
       SCIA        : origin = 0x007050, length = 0x000010     /* SCI-A registers */
       
       NMIINTRUPT  : origin = 0x007060, length = 0x000010     /* NMI Watchdog Interrupt Registers */
       XINTRUPT    : origin = 0x007070, length = 0x000010     /* external interrupt registers */
    
       ADC         : origin = 0x007100, length = 0x000080     /* ADC registers */
    
       I2CA        : origin = 0x007900, length = 0x000040     /* I2C-A registers */
       
       CSM_PWL     : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations. */
    
       PARTID      : origin = 0x3D7FFF, length = 0x000001     /* Part ID register location */
    }
    
     
    SECTIONS
    {
    
    /*** PIE Vect Table and Boot ROM Variables Structures ***/   
      UNION run = PIE_VECT, PAGE = 1
       {
          PieVectTableFile
          GROUP
          {
             EmuKeyVar
             EmuBModeVar
             FlashCallbackVar
             FlashScalingVar
          }
       }
    
    /*** Peripheral Frame 0 Register Structures ***/
       DevEmuRegsFile    : > DEV_EMU,     PAGE = 1
         SysPwrCtrlRegsFile: > SYS_PWR_CTL, PAGE = 1
       FlashRegsFile     : > FLASH_REGS,  PAGE = 1
       CsmRegsFile       : > CSM,         PAGE = 1
       AdcResultFile     : > ADC_RESULT,  PAGE = 1   
       CpuTimer0RegsFile : > CPU_TIMER0,  PAGE = 1
       CpuTimer1RegsFile : > CPU_TIMER1,  PAGE = 1
       CpuTimer2RegsFile : > CPU_TIMER2,  PAGE = 1  
       PieCtrlRegsFile   : > PIE_CTRL,    PAGE = 1      
    
    /*** Peripheral Frame 1 Register Structures ***/      
       ECap1RegsFile     : > ECAP1        PAGE = 1   
       GpioCtrlRegsFile  : > GPIOCTRL     PAGE = 1
       GpioDataRegsFile  : > GPIODAT      PAGE = 1
       GpioIntRegsFile   : > GPIOINT      PAGE = 1
       
    /*** Peripheral Frame 2 Register Structures ***/
       SysCtrlRegsFile   : > SYSTEM,      PAGE = 1
       SpiaRegsFile      : > SPIA,        PAGE = 1
       SciaRegsFile      : > SCIA,        PAGE = 1
       NmiIntruptRegsFile: > NMIINTRUPT,  PAGE = 1
       XIntruptRegsFile  : > XINTRUPT,    PAGE = 1
       AdcRegsFile       : > ADC,         PAGE = 1
       I2caRegsFile      : > I2CA,        PAGE = 1 
                   
    /*** Peripheral Frame 3 Register Structures ***/
       Comp1RegsFile     : > COMP1,       PAGE = 1
       Comp2RegsFile     : > COMP2,       PAGE = 1
       EPwm1RegsFile     : > EPWM1        PAGE = 1   
       EPwm2RegsFile     : > EPWM2        PAGE = 1   
       EPwm3RegsFile     : > EPWM3        PAGE = 1   
       EPwm4RegsFile     : > EPWM4        PAGE = 1   
    
    
    /*** Code Security Module Register Structures ***/
       CsmPwlFile        : > CSM_PWL,     PAGE = 1
    
    /*** Device Part ID Register Structures ***/
       PartIdRegsFile    : > PARTID,      PAGE = 1
    
    }
    
    /*
    //===========================================================================
    // End of file.
    //===========================================================================
    */
    

    IMPORTANT: these files work for NON-BIOS projects.

    In my SYS/BIOS project with the same F2802x_generic_flash.cmd and Headersa_BIOS.cmd (I attach here):

    F2802x_Headers_BIOS_txt.txt
    /*
    //###########################################################################
    //
    // FILE:    F2802x_Headers_BIOS.cmd
    //
    // TITLE:   F2802x Peripheral registers linker command file
    //
    // DESCRIPTION:
    //
    //          This file is for use in BIOS applications.
    //
    //          Linker command file to place the peripheral structures
    //          used within the F2802x headerfiles into the correct memory
    //          mapped locations.
    //
    //          This version of the file does not include the PieVectorTable 
    //          structure. For non-BIOS applications, please use the
    //          F2802x_Headers_nonBIOS.cmd file which includes the PieVectorTable 
    //          structure.
    //
    //###########################################################################
    // $TI Release: F2802x Support Library v3.04.00.00 $
    // $Release Date: Fri Feb 12 19:12:19 IST 2021 $
    // $Copyright:
    // Copyright (C) 2009-2021 Texas Instruments Incorporated - http://www.ti.com/
    //
    // Redistribution and use in source and binary forms, with or without 
    // modification, are permitted provided that the following conditions 
    // are met:
    // 
    //   Redistributions of source code must retain the above copyright 
    //   notice, this list of conditions and the following disclaimer.
    // 
    //   Redistributions in binary form must reproduce the above copyright
    //   notice, this list of conditions and the following disclaimer in the 
    //   documentation and/or other materials provided with the   
    //   distribution.
    // 
    //   Neither the name of Texas Instruments Incorporated nor the names of
    //   its contributors may be used to endorse or promote products derived
    //   from this software without specific prior written permission.
    // 
    // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
    // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
    // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
    // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 
    // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 
    // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 
    // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
    // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
    // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 
    // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 
    // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    // $
    //###########################################################################
    */
    
    MEMORY
    {
     PAGE 0:    /* Program Memory */
    
     PAGE 1:    /* Data Memory */
    
       DEV_EMU     : origin = 0x000880, length = 0x000105     /* device emulation registers */
       SYS_PWR_CTL : origin = 0x000985, length = 0x000003     /* System power control registers */
       FLASH_REGS  : origin = 0x000A80, length = 0x000060     /* FLASH registers */
       CSM         : origin = 0x000AE0, length = 0x000010     /* code security module registers */
    
       ADC_RESULT  : origin = 0x000B00, length = 0x000020     /* ADC Results register */
    
       CPU_TIMER0  : origin = 0x000C00, length = 0x000008     /* CPU Timer0 registers */
       CPU_TIMER1  : origin = 0x000C08, length = 0x000008     /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
       CPU_TIMER2  : origin = 0x000C10, length = 0x000008     /* CPU Timer0 registers (CPU Timer1 & Timer2 reserved TI use)*/
    
       PIE_CTRL    : origin = 0x000CE0, length = 0x000020     /* PIE control registers */
    
       COMP1       : origin = 0x006400, length = 0x000020     /* Comparator 1 registers */
       COMP2       : origin = 0x006420, length = 0x000020     /* Comparator 2 registers */
    
       EPWM1       : origin = 0x006800, length = 0x000040     /* Enhanced PWM 1 registers */
       EPWM2       : origin = 0x006840, length = 0x000040     /* Enhanced PWM 2 registers */
       EPWM3       : origin = 0x006880, length = 0x000040     /* Enhanced PWM 3 registers */
       EPWM4       : origin = 0x0068C0, length = 0x000040     /* Enhanced PWM 4 registers */
    
       ECAP1       : origin = 0x006A00, length = 0x000020     /* Enhanced Capture 1 registers */
    
       GPIOCTRL    : origin = 0x006F80, length = 0x000040     /* GPIO control registers */
       GPIODAT     : origin = 0x006FC0, length = 0x000020     /* GPIO data registers */
       GPIOINT     : origin = 0x006FE0, length = 0x000020     /* GPIO interrupt/LPM registers */
    
       SYSTEM      : origin = 0x007010, length = 0x000020     /* System control registers */
    
       SPIA        : origin = 0x007040, length = 0x000010     /* SPI-A registers */
    
       SCIA        : origin = 0x007050, length = 0x000010     /* SCI-A registers */
    
       NMIINTRUPT  : origin = 0x007060, length = 0x000010     /* NMI Watchdog Interrupt Registers */
       XINTRUPT    : origin = 0x007070, length = 0x000010     /* external interrupt registers */
    
       ADC         : origin = 0x007100, length = 0x000080     /* ADC registers */
    
       I2CA        : origin = 0x007900, length = 0x000040     /* I2C-A registers */
    
       CSM_PWL     : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations. */
    
       PARTID      : origin = 0x3D7FFF, length = 0x000001     /* Part ID register location */
    }
    
    
    SECTIONS
    {
    
    /*** PIE Vect Table and Boot ROM Variables Structures ***/
    /*** The PIE Vector table is called PIEVECT by DSP/BIOS ***/
      UNION run = PIEVECT,                PAGE = 1
       {
          PieVectTableFile     : TYPE=DSECT
          GROUP
          {
             EmuKeyVar         : TYPE=DSECT
             EmuBModeVar       : TYPE=DSECT
             FlashCallbackVar  : TYPE=DSECT
             FlashScalingVar   : TYPE=DSECT
          }
       }
    
    /*** Peripheral Frame 0 Register Structures ***/
       DevEmuRegsFile    : > DEV_EMU,     PAGE = 1
         SysPwrCtrlRegsFile: > SYS_PWR_CTL, PAGE = 1
       FlashRegsFile     : > FLASH_REGS,  PAGE = 1
       CsmRegsFile       : > CSM,         PAGE = 1
       AdcResultFile     : > ADC_RESULT,  PAGE = 1
       CpuTimer0RegsFile : > CPU_TIMER0,  PAGE = 1
       CpuTimer1RegsFile : > CPU_TIMER1,  PAGE = 1
       CpuTimer2RegsFile : > CPU_TIMER2,  PAGE = 1
       PieCtrlRegsFile   : > PIE_CTRL,    PAGE = 1
    
    /*** Peripheral Frame 1 Register Structures ***/
       ECap1RegsFile     : > ECAP1        PAGE = 1
       GpioCtrlRegsFile  : > GPIOCTRL     PAGE = 1
       GpioDataRegsFile  : > GPIODAT      PAGE = 1
       GpioIntRegsFile   : > GPIOINT      PAGE = 1
    
    /*** Peripheral Frame 2 Register Structures ***/
       SysCtrlRegsFile   : > SYSTEM,      PAGE = 1
       SpiaRegsFile      : > SPIA,        PAGE = 1
       SciaRegsFile      : > SCIA,        PAGE = 1
       NmiIntruptRegsFile: > NMIINTRUPT,  PAGE = 1
       XIntruptRegsFile  : > XINTRUPT,    PAGE = 1
       AdcRegsFile       : > ADC,         PAGE = 1
       I2caRegsFile      : > I2CA,        PAGE = 1
    
    /*** Peripheral Frame 3 Register Structures ***/
       Comp1RegsFile     : > COMP1,       PAGE = 1
       Comp2RegsFile     : > COMP2,       PAGE = 1
       EPwm1RegsFile     : > EPWM1        PAGE = 1
       EPwm2RegsFile     : > EPWM2        PAGE = 1
       EPwm3RegsFile     : > EPWM3        PAGE = 1
       EPwm4RegsFile     : > EPWM4        PAGE = 1
    
    
    /*** Code Security Module Register Structures ***/
       CsmPwlFile        : > CSM_PWL,     PAGE = 1
    
    /*** Device Part ID Register Structures ***/
       PartIdRegsFile    : > PARTID,      PAGE = 1
    
    }
    
    /*
    //===========================================================================
    // End of file.
    //===========================================================================
    */
    

    (note: headers files I took from: C:\ti\C2000Ware_3_04_00_00_Software\device_support\f2802x\headers\cmd )

    I have following information:

    Does it mean that I can't write little SYS/BIOS project into F28027F device because it's too large?

  • In SYS/BIOS project this *.cmd file is correct:

    6648.TMS320F28027.txt
    /*
     * Copyright (c) 2015-2020, Texas Instruments Incorporated
     * All rights reserved.
     *
     * Redistribution and use in source and binary forms, with or without
     * modification, are permitted provided that the following conditions
     * are met:
     *
     * *  Redistributions of source code must retain the above copyright
     *    notice, this list of conditions and the following disclaimer.
     *
     * *  Redistributions in binary form must reproduce the above copyright
     *    notice, this list of conditions and the following disclaimer in the
     *    documentation and/or other materials provided with the distribution.
     *
     * *  Neither the name of Texas Instruments Incorporated nor the names of
     *    its contributors may be used to endorse or promote products derived
     *    from this software without specific prior written permission.
     *
     * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
     * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
     * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
     * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
     * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
     * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
     * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
     * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     */
    /*
     *  ======== TMS320F28027.cmd ========
     *  Define the memory block start/length for the F28027
     */
    
    /*
     *  PAGE 0 will be used to organize program sections
     *  PAGE 1 will be used to organize data sections
     *
     *  Notes:
     *        Memory blocks on F2802x are uniform (ie same
     *        physical memory) in both PAGE 0 and PAGE 1.
     *        That is the same memory region should not be
     *        defined for both PAGE 0 and PAGE 1.
     *        Doing so will result in corruption of program
     *        and/or data.
     *
     *        L0 memory blocks are mirrored - that is
     *        they can be accessed in high memory or low memory.
     *        For simplicity only one instance is used in this
     *        linker file.
     */
    
    MEMORY
    {
    PAGE 0:    /* Program Memory */
    
        OTP         : origin = 0x3D7800, length = 0x000400     /* on-chip OTP */
        FLASH       : origin = 0x3F0000, length = 0x007F80     /* on-chip FLASH */
        CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Program with all 0x0000 when CSM is in use. */
        BEGIN       : origin = 0x3F7FF6, length = 0x000002     /* Used for "boot to Flash" bootloader mode. */
        CSM_PWL     : origin = 0x3F7FF8, length = 0x000008     /* CSM password locations in FLASH */
    
        IQTABLES    : origin = 0x3FE000, length = 0x000B50     /* IQ Math Tables in Boot ROM */
        IQTABLES2   : origin = 0x3FEB50, length = 0x00008C     /* IQ Math Tables in Boot ROM */
        IQTABLES3   : origin = 0x3FEBDC, length = 0x0000AA	   /* IQ Math Tables in Boot ROM */
    
        ROM         : origin = 0x3FF27C, length = 0x000D44     /* Boot ROM */
        RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM  */
        VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM  */
    
    PAGE 1 :   /* Data Memory */
    
        M01SARAM    : origin = 0x000000, length = 0x000800     /* on-chip RAM block M0, M1 */
        PIEVECT     : origin = 0xD00,    length = 0x100
        L0SARAM     : origin = 0x008000, length = 0x001000     /* on-chip RAM block L0 */
    }
    
    /*
     *  Allocate sections to memory blocks.
     *  Note:
     *      codestart   user defined section in DSP28_CodeStartBranch.asm
     *                  used to redirect code execution when booting to flash
     *
     *      ramfuncs    user defined section to store functions that will be
     *                  copied from Flash into RAM
     */
    
    SECTIONS
    {
        /* Allocate program areas: */
        .cinit              : > FLASH       PAGE = 0
        .pinit              : > FLASH       PAGE = 0
        .text               : > FLASH       PAGE = 0
        codestart           : > BEGIN       PAGE = 0
        ramfuncs            : LOAD = FLASH      PAGE = 0,
                              RUN  = L0SARAM    PAGE = 1,
                              LOAD_START(_RamfuncsLoadStart),
                              LOAD_SIZE(_RamfuncsLoadSize),
                              LOAD_END(_RamfuncsLoadEnd),
                              RUN_START(_RamfuncsRunStart)
    
        csmpasswds          : > CSM_PWL     PAGE = 0
        csm_rsvd            : > CSM_RSVD    PAGE = 0
    
        /* Allocate uninitalized data sections: */
        .stack              : > M01SARAM | L0SARAM      PAGE = 1
        .ebss               : >> M01SARAM | L0SARAM      PAGE = 1
        .data               : > M01SARAM | L0SARAM      PAGE = 1
        .esysmem            : > L0SARAM | M01SARAM      PAGE = 1
        .cio                : > L0SARAM | M01SARAM      PAGE = 1
    
        /* Initalized sections go in Flash */
        /* For SDFlash to program these, they must be allocated to page 0 */
        .econst             : > FLASH       PAGE = 0
        .switch             : > FLASH       PAGE = 0
        .args               : > FLASH       PAGE = 0
    
    #ifdef __TI_COMPILER_VERSION__
    #if __TI_COMPILER_VERSION__ >= 15009000
        .TI.ramfunc         : {} LOAD = FLASH    PAGE = 0,
                                 RUN  = L0SARAM  PAGE = 1,
                                 table(BINIT)
    #endif
    #endif
    
        /* Allocate IQ math areas: */
        IQmath              : > FLASH       PAGE = 0            /* Math Code */
        IQmathTables        : > IQTABLES    PAGE = 0, TYPE = NOLOAD
    
        /*
         *  Uncomment the section below if calling the IQNexp() or IQexp()
         *  functions from the IQMath.lib library in order to utilize the
         *  relevant IQ Math table in Boot ROM (This saves space and Boot ROM
         *  is 1 wait-state). If this section is not uncommented, IQmathTables2
         *  will be loaded into other memory (SARAM, Flash, etc.) and will take
         *  up space, but 0 wait-state is possible.
         */
        /*
        IQmathTables2       : > IQTABLES2   PAGE = 0, TYPE = NOLOAD
        {
            IQmath.lib<IQNexpTable.obj> (IQmathTablesRam)
        }
        */
    
        /*
         *  Uncomment the section below if calling the IQNasin() or IQasin()
         *  functions from the IQMath.lib library in order to utilize the
         *  relevant IQ Math table in Boot ROM (This saves space and Boot ROM
         *  is 1 wait-state). If this section is not uncommented, IQmathTables2
         *  will be loaded into other memory (SARAM, Flash, etc.) and will take
         *  up space, but 0 wait-state is possible.
         */
        /*
        IQmathTables3       : > IQTABLES3   PAGE = 0, TYPE = NOLOAD
        {
            IQmath.lib<IQNasinTable.obj> (IQmathTablesRam)
        }
        */
    }
    

    BUT THE MOST IMPORTANT IS TO CHECK THAT CHECBOX IN BOOT OPTIONS: 

    After that my program fired from flash... but another problems happened and I described it in another thread.