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TMS320F280041: ISR for Simultaneous ADC sampling

Lennart Gardian2
Intellectual 270 points
Part Number: TMS320F280041

Hi there,

I'm trying to figure out how the ISRs are being called when I use trigger two ADCs from the same SOC event. According to my understanding of how this works I setup ADC A and B to the same SOCA event from the ePWM module:

AdcaRegs.ADCSOC0CTL.bit.TRIGSEL = 5;   // Trigger on ePWM1 SOCA
AdcbRegs.ADCSOC0CTL.bit.TRIGSEL = 5;   // Trigger on ePWM1 SOCA

From the ADC example I assume that these two lines

AdcaRegs.ADCINTSEL1N2.bit.INT1SEL = 0; // End of SOC0 will set INT1 flag
AdcaRegs.ADCINTSEL1N2.bit.INT1E = 1; // Enable INT1 flag

cause the jump to the <p>adcA1ISR</p> interrupt service routing. My problem now is that I would like to make sure that the EOC happened for ADC B as well and that if I read the result register in the ISR for ADC A and B they are both updated. Is there any possibility to logic AND connect the EOC0 events for ADC A and B and have the interrupt triggered accordingly? 

Thanksin advance for your help,

Lennart

  • 0
    TI__Guru 60865 points

    Hi Lennart,

    You can also enable the INT1 flag on ADC-B (same code as you've posted, but AdcbRegs instead of AdcaRegs) and then in the ADC-A ISR:

    • Check that ADC-B INT1 has been set
    • Clear ADC-B INT1 

    I don't think you want/need to take two ISRs

  • 0
    Intellectual 270 points

    Hi Devin,

    I was afraid that would be the answer. I clearly would like to avoid to use two ISRs but waiting in an ISR for another ISR is also kinda ougly. Isn't the purpose of ISR so I don't have to WAIT for an event but rather be able to react on it whenever it occurs?
    Anyway, in my example it should be fine as ADC-A and B will be done at a very similar time instance so there probably will not be much time to wait for. However I thought the hardware would probably implement a "nicer" way to get this done like the PIE vector checking two events before triggering the interrupt in the CPU.

  • +1 in reply to Lennart Gardian2
    TI__Guru 60865 points

    Hi Lennart,

    I don't think you should be waiting in the ISR; as long as you select the ISR to be triggered by the longest sampling path (ADC with the most SOCs) then you should just check the ADCINT flag(s) from the other ADC(s) and pass or fail.  If they are already set at the beginning of the ISR, the sanity check is passed, or if they aren't set, then something is wrong with the configuration and the check fails.  

  • 0
    Intellectual 270 points

    ah ok. considering it just a sanety check makes it sound better. However, I don't have a channel that takes longer than the other. They both have to handle the same amount of SOCs with all having the same acquisition window. Hence I'd expect them to take exactly the same amount of time.
    But I think with the time added by the sanety check (which sure makes sense) Both ADC should be done even though one ADC takes a tiny bit longer than the one triggering the ISR.

    Thanks for you help. I'll come back to you if it doesn't work as expected ;)

  • 0 in reply to Lennart Gardian2
    TI__Guru 60865 points

    Hi Lennart,

    If you have the same number of SOCs, you can pick any ADC to trigger the ISR (you are correct that times could theoretically be different if parallel SOCs use different S+H durations, but it is generally recommended to have parallel SOCs use the same acquisition window duration for multiple reasons, which you are already doing). In that case, both ISR flags should get set at exactly the same time.  Since the context switch to the ISR is caused by one flag going high, and the switch takes some time, you can assume that the other flag(s) should be set before the ISR starts running any checking code. 

    Also don't forget to clear the additional flags, otherwise your check will always succeed after the 1st iteration.  

  • 0 in reply to Devin Cottier
    Intellectual 270 points

    Hi Devin,

    thanks for the further details and  the reminder. I should be all set then.