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TMS320F280023: Problem in generating PWM waveform

Part Number: TMS320F280023

Dear team:

One of my client  want to generate PWM waveform as show in the below picture:

He hopes:
The AQCTLA register sets epwmA high when the time base count value is 0, and sets epwmA low when the time base count value is CMPA;
The AQCTLB register sets epwmB high when the time base count value is PRD, and sets epwmB low when the time base count value is CMPB.
But in the end, a PWM wave with the same frequency and duty cycle and the same phase is generated as shown in below picture:

May I ask what is wrong with this setting? Below is his code:

Initialization part:

       EPwm1Regs.TBPRD = p->PERIOD;

       EPwm1Regs.TBPHS.all = 0;

       EPwm1Regs.TBCTR = 0x0000;

 

       EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; //递增递减计数模式

       EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;         //禁止TBPHS加载到TBCTR

       EPwm1Regs.TBCTL.bit.PRDLD = TB_SHADOW;

      

       EPwm1Regs.EPWMSYNCINSEL.all = 0;

       EPwm1Regs.EPWMSYNCOUTEN.all = 0;

       EPwm1Regs.TBCTL2.bit.OSHTSYNCMODE = 0;

       EPwm1Regs.TBCTL.bit.CLKDIV = 0;           //时间基准时钟预分频位

       EPwm1Regs.TBCTL.bit.HSPCLKDIV = 0;       //高速时间基准时钟预分频位

       EPwm1Regs.TBCTL.bit.FREE_SOFT = 11;    

 

       EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;

       EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;

       EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;

       EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;

 

       EPwm1Regs.AQCTL.bit.SHDWAQAMODE = 0;

       EPwm1Regs.AQCTL.bit.SHDWAQBMODE = 0;

 

       EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;

       EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;

 

       EPwm1Regs.AQCTLB.bit.PRD = AQ_SET;

       EPwm1Regs.AQCTLB.bit.CBD = AQ_CLEAR;

 

       EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;

/*====================================================================*/

       EPwm1Regs.CMPA.bit.CMPA = p->CMPRA;

       EPwm1Regs.CMPB.bit.CMPB = p->CMPRB;

/*====================================================================*/

       EALLOW;

      CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1;

       EDIS;

PWM sitting:

       EPwm1Regs.AQCTLA.bit.ZRO = AQ_SET;

       EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;

 

       EPwm1Regs.AQCTLB.bit.PRD = AQ_SET;

       EPwm1Regs.AQCTLB.bit.CBD = AQ_CLEAR;

 

       EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;

       EPwm1Regs.DBFED.all = 100;

       EPwm1Regs.DBRED.all = 100;

 

       EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HI;

 

       EPwm1Regs.AQCSFRC.bit.CSFA = 0;

       EPwm1Regs.AQCSFRC.bit.CSFB = 0;

Best regards

  • that is just phase shifted EPWMs. You can use different EPWM modules to achieve this or if you want to go with your settings.

    COUNTER MODE = UP-DOWN COUNT MODE

    AQ

    CNT=0, A output HIGH, B output DO NOTHING

    CNT=CMPA, COUNTER counting up, A output LOW, B output DO NOTHING

    CNT=PRD, B output HIGH, A output DO NOTHING

    CNT=CMPB, COUNTER counting DOWN, B output LOW, A output DO NOTHING

    Nima

  • Dear Nima:

    Thank you for your reply.

    It seems that my client's sittings are the same as you said. But why is the output of PWM1B synchronized with PWM1A?

    Best regards

  • Please request them so specify the actions for the rest of the events.

    Another thing to try is setting the actions to what they need to be instead of "DO NOTHING"

    For example for OUTPUT A, CTR=PRD clear output low. CTR=CMPAD clear output low, etc.

    Nima