C2000 microcontrollers forum - Recent Threads

TMS320F2800137: VDDIO-BOR threshold

Wiky Liao — Sun, 14 Jun 2026 12:45:41 GMT

Part Number: TMS320F2800137
Other Parts Discussed in Thread: MSPM0C1105

Hi Expert,

In VDDIO-BOR circuit, we can see it covers two threshould: BOR-VDDIO-UP and BOR-VDDIO-DOWN, from my understanding it is used in power up and power down seperately, that means:

During power up, when VDDIO voltage meet BOR-VDDIO-UP value, the device will release XRSn and start to work.
During power down, when VDDIO voltage meet BOR-VDDIO-DOWN value, the device will hold XRSn with Low.

From my understand, BOR-VDDIO-UP should be larger than BOR-VDDIO-DOWN, to avoid un-wanted level jumping. In TI other MCU like MSPM0C1105, BOR-UP also higher than BOR-DOWN:

However in F2800137 datasheet, BOR-UP is 2.7V while BOR-DOWN is 2.81V min and 3.0V max, if user application VDDIO is fix 2.9V, that would make the chip trig the BOR-UP and BOR-DOWN continuously, that seems not acceptable for end customer, what's the key purpose of this design? Could you explain more detail of this BOR mechanism? Thanks.

Wiky

TMS320F28P650DK: Random issues Debugging + Flashing

Ayden Bourdeau — Sat, 13 Jun 2026 13:53:57 GMT

Part Number: TMS320F28P650DK
Other Parts Discussed in Thread: UNIFLASH

Hello,

Up until fairly recently I have had no problems on a custom board with the P65x. A few weeks ago I began development on a SSBL and noticed that a bunch or issues arrose with debugging and flashing the controller after 4-6 months of no problems.

lash banks that the user would like the flash plugin to erase (in the CPU1 flash plugin GUI and the CPU2 flash plugin GUI)
C28xx_CPU1: Warning: Failed unlocking device (zone 1) after reset.
C28xx_CPU1: Warning: Failed unlocking device (zone 2) after reset.
C28xx_CPU1: Trouble Setting Breakpoint with the Action "Remain Halted" at 0x10058: (Error -1066 @ 0x10058) Unable to set/clear requested breakpoint. Verify that the breakpoint address is in valid memory. (Emulation package 20.0.0.3283)
C28xx_CPU1: Breakpoint Manager: Retrying with a AET breakpoint
C28xx_CPU1: GSxMSEL register configured correctly
C28xx_CPU1: BankMuxSel register configured correctly
C28xx_CPU1: Trouble Setting Breakpoint with the Action "Remain Halted" at 0x1010c: (Error -1066 @ 0x1010C) Unable to set/clear requested breakpoint. Verify that the breakpoint address is in valid memory. (Emulation package 20.0.0.3283)
C28xx_CPU1: Breakpoint Manager: Retrying with a AET breakpoint
C28xx_CPU1: Error executing PLL configuration algorithm. Operation cancelled. (0x0)
C28xx_CPU1: Perform a debugger reset and execute the Boot-ROM code (click on the RESUME button in CCS debug window) before erasing/loading the Flash. If that does not help to perform a successful Flash erase/load, check the Reset cause (RESC) register, NMI shadow flag (NMISHDFLG) register and the Boot-ROM status register for further debug.
C28xx_CPU1: File Loader: Memory write failed: Unknown error
C28xx_CPU1: Breakpoint Manager: Retrying with a AET breakpoint

After doing some research, it looks like the device cannot unlock specific zones in flash to program but I have never worked with the DCSM? It seems the only way to fix this is to perform a bunch of memory operations via Uniflash (don't know why this works is it a different GEL file maybe?) like erasing all of flash and reflashing several times and if I am lucky it will recover. I also noticed that most of the scripts on Uniflash require me to manually reset the controller with our push button or else they hang on OnTargetConnect().

I tried to revert all my changes from _cint00 and the linker cmd file back to what they were and now none of my projects can load or flash.

Any suggestions on how to proceed with debugging if / how the device was locked would be great. I followed the instructions in a similar forum with no success.

https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1066378/tms320f280049-trouble-setting-breakpoint-with-the-action-remain-halted-at-0xc0d4

TMS320C6655: Nor flash device open fail

Fartine Tripoli — Sat, 13 Jun 2026 08:42:02 GMT

Part Number: TMS320C6655

Hi,

I'm using MT25QU128ABA nor flash device with TMS320C6655. Nor flash is upgraded in remote in Nor boot always. The platform device open fails intermittently. can you suggest a way to troubleshoot the issue?

Regards,

Fartine.

TMS320F28P650DK: EtherCAT: Failed to upload SDO when final address is odd

Jianyu Wang — Sat, 13 Jun 2026 07:50:20 GMT

Part Number: TMS320F28P650DK

Hi TI experts,

We have an application that we use TMS320F28P650DK to replace our old product. We found an issue that the new device cannot go OP using the old XML.

We identify the issue is that, the EtherCAT Master cannot read the SDO response if SM1 length is Odd.

The configuration of our old xml is like follows,

The start address of SM1 is 0x1110 and length is 253. The final byte is odd address. When the length is changed to 252, then the drive can go OP.

We are using beckhoff SSC stack. In function MBX_CopyToSendMailbox() in file mailbox.c, there is HW_EscWriteWord(u16dummy,(u16EscAddrSendMbx + u16SendMbxSize - 2));

that writes final dummy byte to SM1. We are able to identify that, if (u16EscAddrSendMbx + u16SendMbxSize - 2) is even, ESC register 0x80c, memory 0x50406 becomes 0x0232, that successfully read by host, after this line is executed.

Buf if (u16EscAddrSendMbx + u16SendMbxSize - 2) is odd, memory 0x50406 stays 0x8032, that SM1 is still in written. Which blocks host to read the SDO response.

This is a quite important application that some of the customers are reluctant to change XML, as old drives are still in use.

TMS320F280039: MPPT DEBUG

Jack Tan80 — Sat, 13 Jun 2026 01:05:51 GMT

Part Number: TMS320F280039
Other Parts Discussed in Thread: SFRA

Dear c2000 expert,

I'm using ti's solar library in my projects. Here is my project infomation:

- Topology: BOOST, pv input: 270V~634V, output voltage: 700V~800V(Output connect to baterry)

-Switch freq: 50Khz

-Inner inductor current loop runs at 25khz

-Out pv voltage loop runs at 6.25khz

-MPPT runs at 62.5hz

The inner current loop is stable, because the current loop coef are generated by using sfra tools, and the bandwith is about 2khz. I'm using mppt_incc in my project, currently I found that the time of chasing max power point takes about several minutes, and it has overshoot issue. Can you share some suggestion on how to improve the mppt performance? I'd like to shorten the time of chasing max power point and fix the overshoot.

Regards,

Jack

TMS320F28069F: Thanks for all your help!

Dave Reagan — Fri, 12 Jun 2026 20:06:44 GMT

Part Number: TMS320F28069F

Hello All,

We recently released a Dental Electric Handpiece (for drilling caries, and endodontics). The motor is controlled mostly by Instaspin. I'd like to thank you folks for helping me out again and again, over the last 3 or 4 years - especially
Yanming Luo, Matthew Pate, Jason Osbourne and Ki. There were several hurdles I could not have gotten over without you! Thanks again!
Best Regards,

Dave Reagan

TMS320F28069M: TMS320F28069M BiSS-C via SPI with POSMGR

James Hammers — Fri, 12 Jun 2026 19:08:14 GMT

Part Number: TMS320F28069M
Other Parts Discussed in Thread: BOOSTXL-POSMGR, LAUNCHXL-F28069M, TIDM-1010

Hi Ti team,

I am working on a motor control application and need to read the position from a BiSS-C absolute encoder. My current hardware setup consists of the LAUNCHXL-F28069M and the BOOSTXL-POSMGR (TIDM-1010).

I am aware that the F28069M does not feature the Configurable Logic Block (CLB) required for full BiSS-C compliance and hardware line-delay compensation. However, I do not need bidirectional communication or the ability to read/write to the encoder's internal registers. I strictly only need to read the Single-Cycle Data (SCD) to get the motor position.

Because the BOOSTXL-POSMGR acts as the physical RS-485 transceiver layer, my plan is to manually jumper the required lines between the LaunchPad and the BoosterPack:

Power / GND / Enable to power the board and encoder.
TxEN tied to a GPIO and held low.
SPI MISO (or equivalent) connected to the SL data line to receive the response.
SPI CLK (or a PWM output) connected to the MA clock line to drive the encoder.

Knowing that I am intentionally bypassing the CLB and only going for a unidirectional read, I have a few questions about implementing this workaround on the F28069M:

Clock Speed and Delay: Without hardware delay compensation, how slow will I need to run the MA clock (e.g., 2 MHz or lower) to ensure the SPI samples the returning data correctly?
Cable Length Limits: Assuming I lower the clock speed to compensate, what is the practical maximum cable length I can expect to achieve before the propagation delay causes the SPI to read corrupted data?
Word Length Constraints: BiSS-C frames (Position + Error + Warning + CRC) often exceed the standard 16-bit or 32-bit SPI word limits. What is the recommended software approach on the F2806x's SPI peripheral to capture a continuous 40+ bit frame without introducing gaps in the clock signal that might violate the BiSS-C timeout rules?

Any guidance, known limitations, or code snippets from others who have successfully implemented this unidirectional SPI workaround on older Piccolo devices would be greatly appreciated.

Thank you!

TMS320F28P551SG: How to display CLB diagram with CCS V20.4

Jeffrey Jin — Fri, 12 Jun 2026 18:32:59 GMT

Part Number: TMS320F28P551SG

Hi Expert,

It's not an issue to display CLB diagram before CCS V20.x, which is set GENERATE_DIAGRAM = 1 in CCS Build.

But CCS V20.x remove such setting. Thefere, I do not know where to set it.

Would you please find it ASAP ?

Thanks,

Jeffrey Jin

TMS320F280049C: TIDM‑HV‑1PH‑DCAC Gate Driver Daughter Board BOM and Schematic Request

Ciyuan Zhang — Fri, 12 Jun 2026 15:18:31 GMT

Part Number: TMS320F280049C

Hello,

We are working with the TIDM‑HV‑1PH‑DCAC (Voltage Source Inverter Reference Design, Rev. E) and reviewing the available hardware design files. Link: Voltage Source Inverter Reference Design (Rev. E)

While the main inverter board schematic and BOM are available, we are unable to locate the BOM and schematic for the gate driver daughter board used in this design.

From the inverter schematic, we have identified that TLP350 optocouplers are used in the gate drive stage. However, we are looking for the complete daughter board design, including schematic, BOM, or any related documentation.

Could you please confirm whether these design files are available, or provide guidance on how to obtain them?

Thank you.

SYSCONFIG: Duplicate GPIO Definitions in board.h (SysConfig- auto generated)

Thao Truong — Fri, 12 Jun 2026 14:00:33 GMT

Part Number: SYSCONFIG

I'm working with the example project led_ex2_blinky_cpu1_cpu2_cpu3_multi for the F29H85x (Multi-Core) and have discovered an issue with the automatically generated board.h files from SysConfig.

The board.h file for CPU1 is correct, but the board.h files for CPU2 and CPU3 contain duplicate GPIO definitions.

//*****************************************************************************

// GPIO Configurations

//*****************************************************************************

#define CPU2_LED 9

void CPU2_LED_init();

#define CPU3_LED 23

void CPU3_LED_init();

//*****************************************************************************

// CMPSS Configurations

//*****************************************************************************

// RTDMA1 Configurations

//*****************************************************************************

// RTDMA2 Configurations

//*****************************************************************************

// GPIO Configurations

//*****************************************************************************

#define CPU2_LED 9

void CPU2_LED_init();

#define CPU3_LED 23

void CPU3_LED_init();

Questions:

Why does SysConfig generate duplicate #define statements in the CPU2 and CPU3 board.h files?
Is this a known issue or an error in the SysConfig configuration of this example project?
How should this issue be resolved?
Why doesn't the compiler detect and warn about these duplicate #define statements?

TMS320F28388D: Secure BOOT on C2000 Device

Deepti T — Fri, 12 Jun 2026 13:59:45 GMT

Part Number: TMS320F28388D

I want to understand the secure boot application. as mentioned in article 400msec why additional time is taken. If we change the internal oscillator can the additonal time be reduced.TMS320 Secure Boot.pdf

TMS320F28P550SJ: FSI communication instability between F28P650 and F28P550 (single data lane, asymmetric failure P650→P550)

Phil Lee — Fri, 12 Jun 2026 10:33:01 GMT

Part Number: TMS320F28P550SJ

Issue Description

We are experiencing an asymmetric FSI communication issue between two C2000 devices:

DSP1: F28P550SJ6
DSP2: F28P650DK6

Hardware Configuration

Connection signals (both directions):
- FSIRXA_CLK
- FSIRXA_D0
- FSITXA_CLK
- FSITXA_D0
Only one data lane (D0) is used (no D1)
Optional digital isolator is present between devices in some tests

FSI TX Clock Configuration

F28P550 → TX frequency: 37.5 MHz
F28P650 → TX frequency: 5 MHz

Observed Behavior

P550 → P650 transmission
- Communication is always correct and stable
P650 → P550 transmission
- Communication frequently fails
- Data loss or frame errors observed
The issue occurs:
- With or without isolator
- Independent of connection path

Question

Has anyone encountered a similar issue with asymmetric FSI communication reliability between F28P650 and F28P550?

Even after adding a delay line on the P550 receiver side, the issue could not be resolved.

Any suggestions or debugging recommendations would be greatly appreciated.

LAUNCHXL-F280039C: BOOTLOADER for 2 MCU via PC

TRUONG NHAT PHAN — Fri, 12 Jun 2026 08:07:30 GMT

Part Number: LAUNCHXL-F280039C
Other Parts Discussed in Thread: TMS320F280039C

Hello Experts,

Currently, my circuit have 2 MCU TMS320F280039C and I am implementing the bootloader for these MCUs with structure PC --> (SCIA)MCU1(SCIB) --> (SCIA)MCU2. I use serial flash programmer from TI to do 2 steps as below:

Step1: PC will boot MCU1 via SCIA. I follow as TI guiline "Serial Flash Programming of C2000™ Microcontrollers" and I can implement bootloader for MCU1 OK

Step2: PC will boot MCU2 via MCU1. In this case, MCU1 will be a UART brigde, just get signal from PC via SCIA and SCIB will get signal from SCIA after that transfer to MCU2 as below:

rxStatus1 = SCI_getRxStatus(SCIA_BASE);
rxStatus2 = SCI_getRxStatus(SCIB_BASE);
if(rxStatus1 || rxStatus2)
{
while(!SCI_isDataAvailableNonFIFO(SCIA_BASE) && !SCI_isDataAvailableNonFIFO(SCIB_BASE))
{
}

if(SCI_isDataAvailableNonFIFO(SCIA_BASE) == 1)
{
receivedChar1 = ((uint16_t)(HWREGH(SCIA_BASE + SCI_O_RXBUF) & SCI_RXBUF_SAR_M));
SCI_writeCharNonBlocking(SCIB_BASE, receivedChar1);
}
if(SCI_isDataAvailableNonFIFO(SCIB_BASE) == 1)
{
receivedChar2 = ((uint16_t)(HWREGH(SCIB_BASE + SCI_O_RXBUF) & SCI_RXBUF_SAR_M));
SCI_writeCharNonBlocking(SCIA_BASE, receivedChar2);
}
}

I also use TI guiline "Serial Flash Programming of C2000™ Microcontrollers" to do bootloader for MCU2. However, sometimes the command prompt indicate 0xAA = 0xAA and PC cannot send command to MCU2 in the next command as below picture. Please help me sharing your suggestions.

Thank you

TMS320F28388D: USB ECM (Ethernet Control Model) protocol on the F28388D

Leo Wu — Fri, 12 Jun 2026 02:31:54 GMT

Part Number: TMS320F28388D
Other Parts Discussed in Thread: C2000WARE

Hi experts,

My customer have questions on the USB development.

Problem Description: In order to achieve more efficient network data transfer, I would like to use the USB ECM (Ethernet Control Model) protocol on the F28388D. However, in the current C2000Ware examples, only CDC-ACM (virtual serial port) related examples are available.

Requirement: Could TI officially provide an ECM protocol stack or related driver support for the F28388D USB peripheral? Or is there a plan to include this protocol stack in a future release?

Thanks

TMS320F28388D: McBSP MFSR and MFSX not synced

Vi Phan — Thu, 11 Jun 2026 23:50:24 GMT

Part Number: TMS320F28388D

I tried to set up the McBSP to have both TX and RX use the same pin for FS and CLK which are MFSX and MCLKX.

It doesn't seem to me that RX side can be triggered using MFSX and MCLKX. I setup the config to work around that by using sample rate generator to generate TX and supply RX.

The problem I have is that the MFSX pin and MFSR pin are not synced. I see that the MFSX and MFSR are 700ns apart.

Here is my config:

McbspbRegs.SPCR2.bit.FRST = 0;

McbspbRegs.SPCR2.bit.GRST = 0;

McbspbRegs.SPCR2.bit.XRST = 0;

McbspbRegs.SPCR1.bit.RRST = 0;

McbspbRegs.SPCR1.bit.RJUST = 0;

McbspbRegs.RCR2.bit.RDATDLY = 1;

McbspbRegs.XCR2.bit.XDATDLY = 0;

McbspbRegs.RCR1.bit.RWDLEN1 = 2;

McbspbRegs.XCR1.bit.XWDLEN1 = 2;

McbspbRegs.PCR.bit.CLKXM = 1;

McbspbRegs.PCR.bit.CLKRM = 1;

McbspbRegs.PCR.bit.FSXM = 1;

McbspbRegs.PCR.bit.FSRM = 1;

McbspbRegs.SRGR2.bit.FSGM = 1;

/// Clock related

McbspbRegs.SRGR1.bit.CLKGDV = 9;

McbspbRegs.SRGR2.bit.FPER = 32;

McbspbRegs.SRGR1.bit.FWID = 0;

/// clock source

McbspbRegs.SRGR2.bit.CLKSM = 1;

McbspbRegs.PCR.bit.SCLKME = 0;

McbspbRegs.SRGR2.bit.GSYNC = 0;

McbspbRegs.MFFINT.bit.RINT = 1;

__asm(" RPT #80 || NOP");

McbspbRegs.SPCR2.bit.GRST = 1;

McbspbRegs.SPCR2.bit.FRST = 1;

__asm(" RPT #160 || NOP");

McbspbRegs.SPCR2.bit.XRST = 1;

McbspbRegs.SPCR1.bit.RRST = 1;

TMS320F280039C: Missing Gate Driver Daughter Board

Zoran Mihajlovic — Thu, 11 Jun 2026 19:39:42 GMT

Part Number: TMS320F280039C
Other Parts Discussed in Thread: TIDM-HV-1PH-DCAC

The TIDM-HV-1PH-DCAC reference design is missing a gate driver daughter board information. To complete the design, we're looking for the daughter board's reference design and respective BOM, Please advise.

Thank you.

TMS320F28027: Request for Schematic, Gerber Files, and Hardware Availability of PSFB DC/DC Converter Reference Design

Prasanna Naik — Thu, 11 Jun 2026 14:47:43 GMT

Part Number: TMS320F28027
Other Parts Discussed in Thread: PMP23126

I have gone through the Phase-Shifted Full Bridge (PSFB) DC/DC Power Converter Design Guide. We tried to gather the design data; however, we were unable to access the required information.

I also attempted to access the links and reference data provided in the design guide/manual, but they were not available.

Could you please share the schematic files and Gerber files and software files? These files would be very helpful for our development and evaluation activities.

Additionally, if the reference hardware or evaluation board is available, please share with the purchase link

F29H85X-SDK: Issue with JTAG connection on F29H85x-SOM-EVM

Sophia Rüth — Thu, 11 Jun 2026 14:03:16 GMT

Part Number: F29H85X-SDK
Other Parts Discussed in Thread: HSEC180ADAPEVM, TMDSHSECDOCK, F29H85X-SOM-EVM

Hello,

I am using the F29H85X-SOM-EVM with the HSEC180ADAPEVM, TMDSHSECDOCK and XDS110 Debug Probe. I have been using the SDK Examples (v26.0) and modified some of them to try out some functionality.

After Flashing and starting to Debug a minor change to one of my examples (modified from freertos_ssu_demo), the JTAG connection stopped working. If I try to connect to target, I get
"CS_DAP_0: Error connecting to the target: (Error -1170 @ 0x0) Unable to access the DAP. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 20.5.0.3902) ".

Resetting and power-cycling the board had no effect and lowering TCLK also did not change anything.

If I test the Debug Probe connection in the target configuration, this is the output:

-----[Print the board config pathname(s)]------------------------------------ C:\Users\xxx\AppData\Local\TEXASI~1\
CCS\ccs2050\0\0\BrdDat\testBoard.dat

-----[Print the reset-command software log-file]-----------------------------
This utility has selected a 100/110/510 class product.
This utility will load the adapter 'jioxds110.dll'.
The library build date was 'Mar 4 2026'.
The library build time was '18:13:05'.
The library package version is '20.5.0.3902'.
The library component version is '35.35.0.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '5' (0x00000005).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.

-----[Print the reset-command hardware log-file]-----------------------------
The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the XDS110 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for XDS110 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).

-----[An error has occurred and this utility has aborted]--------------------
This error is generated by TI's USCIF driver or utilities.

The value is '-233' (0xffffff17).
The title is 'SC_ERR_PATH_BROKEN'.

The explanation is:
The JTAG IR and DR scan-paths cannot circulate bits, they may be broken.
An attempt to scan the JTAG scan-path has failed.
The target's JTAG scan-path appears to be broken with a stuck-at-ones or stuck-at-zero fault.

Is there anything I can do to further debug and recover this?
Thank you!

TMS320F28P650DK: The DesignDRIVE support for F28P650

Zhang Liang — Thu, 11 Jun 2026 13:59:12 GMT

Part Number: TMS320F28P650DK

Hi,

Please advise if the F28P650(TMDSCNCD28P650X) can support the DesignDEIVE IDDK, thanks.

C2000WARE: Empty lab in wrong folder

Guilherme Márcio Soares CNPq 304981/2025-7 — Thu, 11 Jun 2026 13:14:30 GMT

Part Number: C2000WARE

Hi, I noticed that empty_lab and empty_ipc_lab are not located in the correct folders when I access them through the Resource Explorer in CCS Theia.

TMS320F28P551SG: F28P551 control card schematic

Zane Wei — Thu, 11 Jun 2026 07:45:58 GMT

Part Number: TMS320F28P551SG
Other Parts Discussed in Thread: C2000WARE

Hi Team,

Could you help provide the right link, which can download F28P551 control card schematic? Thanks!

This link C:\ti\c2000\C2000Ware_26_01_00_00\boards\controlCARDs\TMDSCNCD28P551X\RevA\design files(www.ti.com/.../SLVC881) is not work.

Best Regards,

Zane

[FAQ] TMS320F28P650DK: Ethercat Important Documentation.

Kunal Wasnik — Thu, 11 Jun 2026 06:45:07 GMT

Part Number: TMS320F28P650DK

Understanding Ethercat:

Introduction to Ethercat by Beckhoff : EtherCAT Introduction
ETG.2200 EtherCAT, EtherCAT P and Safety over EtherCAT Slave Implementation Guide
Section I - Technology
Register Description : Section II - Register Description
Section III - ET1100 Hardware Description

Troubleshooting

Appnote : F28P65 + DP83826 EtherCAT Frame Error Investigation Methods and Application Recommendations
ETG ethercat_diagnosis_for_users : ETG Template PPT
Beckhoff App Note : Application Note

Docs / Troubleshooting related to running ethercat program.

For F28P65x / F2838x Devices

EtherCAT_SubordinateDevice_Controller_Software_User_Guide : "{c2000 sdk directory}\libraries\communications\Ethercat\{device_name}\docs"
Examples : {c2000 sdk directory}\libraries\communications\Ethercat\{device_name}\examples
Launchpad not going to op mode : LAUNCHXL-F28P65X: Help needed: TI C2000 F28P65x EtherCAT slave (CPU1 Echoback) not reaching OP state in TwinCAT 3 - C2000 microcontrollers forum - C2000™︎ microcontrollers - TI E2E support forums
Dc Sync Example Cycle time measurements : TMS320F28P650DK: Low-level interval output when running "f28p65_cpu2_echoback_solution" example - C2000™︎ microcontrollers - INTERNAL forum - C2000™︎ microcontrollers - INTERNAL - TI E2E support forums
Running Echoback Example on cpu2 (multicore): TMS320F28P650DK: Cannot be scanned in TwinCAT when running "f28p65x_cpu2_echoback_solution" demo codes on F28P65x launchpad - C2000™︎ microcontrollers - INTERNAL forum - C2000™︎ microcontrollers - INTERNAL - TI E2E support forums
Unpredictable Behaviour of Twincat sometimes not able to scan device after reset : TMS320F28P650DK: EtherCAT Slave Initialization - C2000 microcontrollers forum - C2000™︎ microcontrollers - TI E2E support forums
Not being able to detect forward rx errors : TMS320F28388S: ESC register 0x300 count exception - C2000™︎ microcontrollers - INTERNAL forum - C2000™︎ microcontrollers - INTERNAL - TI E2E support forums
Not able to detect sync , pwm signals for dc sync example of sdk on control card: in ethercat_dc_eepromemu_subdevice_cpu1_hal.c file , move the following configure before the launchpad definition.
Configure only 1 port for ethercat : TMS320F28P650DH: Can only configure ESC port0 GPIO without configure Port1 gpio? - C2000 microcontrollers forum - C2000™︎ microcontrollers - TI E2E support forums

For F29H85x devices

Docs : {f29sdk}\docs\Getting_Started.html
Example : {F29sdk}\examples\communication\Ethercat\examples

TMS320F28P650DK: EtherCAT Slave Stack Code (SSC) download

Wilson Liang2 — Thu, 11 Jun 2026 04:17:06 GMT

Part Number: TMS320F28P650DK

Hi Sir

I would like to verify the EtherCAT functionality on the EVM. However, the provided example does not include the SSC (Slave Stack Code). Could TI provide it? Thank you!

C2000-C-GANG-SW: Supports older versions of C2000-GANG software

Wilson Liang2 — Thu, 11 Jun 2026 03:14:46 GMT

Part Number: C2000-C-GANG-SW
Other Parts Discussed in Thread: C-GANG

Hi Sir

Only the C-GANG software is currently available for download on the TI official website. Could you please let me know if there are any updates for the C2000-GANG TOOLS software, or if there is a download path for older versions?

Thank you.

TMS320F2800137: Maximum Allowed Filter Capacitance for External Precision Resistor

Matthew Bavier — Wed, 10 Jun 2026 18:31:41 GMT

Part Number: TMS320F2800137

Hi,

I saw in the datasheet it is recommended to use 10 nF for the ExtR decoupling capacitance, but I was wondering if there were any concerns with using a higher capactiance such as 100 nF?

Thank you,

Matthew Bavier