C2000 microcontrollers forum - Recent Threads

TMS320F28P650DK: Confirming latest C2000Ware/driverlib files for TMS320F28P650DK9

Elliot Serfaty — Thu, 24 Sep 2026 11:45:31 GMT

Part Number: TMS320F28P650DK
Other Parts Discussed in Thread: C2000WARE, SYSCONFIG

Hello,

I'm new to the C2000 ecosystem and TI microcontrollers in general, so please excuse if some of this is basic.
I want to make sure I'm working from the most current and correct files before going further.

I'm working on a real-time motor drive application built on the TMS320F28P650DK9. Here is what I currently have installed/configured:

Device: TMS320F28P650DK9 (package 256ZEJ)
C2000Ware: 5.04.00.00
C2000Ware MotorControl SDK: 5.04.00.00
SysConfig: 1.24.0 (project) , though one of my build scripts still references sysconfig 1.23.1, which I'm not sure is expected
Compiler: ti-cgt-c2000 22.6.1.LTS
Code Composer Studio: installed under a "ccs1271" folder (I believe this corresponds to CCS 12.7.1, but I'm not 100% sure how to confirm the exact CCS version)

My questions:

Are C2000Ware 5.04.00.00 and MotorControl SDK 5.04.00.00 still the latest releases for the TMS320F28P650DK9, or has a newer version been released with updated device headers/driverlib for this part?
Is there a recommended/compatible SysConfig version I should standardize on for this device (I noticed a version mismatch between 1.24.0 and 1.23.1 in my project files)?
Are there any known errata, advisories, or recently updated device support files (driverlib, linker command files, boot files) specific to the F28P650DK9 that I should be aware of?
As someone new to this platform, is there a recommended way to check for/subscribe to update notifications for C2000Ware and device-specific files going forward?

Any guidance, including pointers to documentation for beginners, would be greatly appreciated.

Thank you!

AM2612: DCAN--Peripheral functions

Yelena Mao — Thu, 24 Sep 2026 10:44:04 GMT

Part Number: AM2612

DCAN--Peripheral functions.docx

TMS320F280036C-Q1: CCSI over CLB

Kita Li — Wed, 23 Sep 2026 15:26:24 GMT

Part Number: TMS320F280036C-Q1

Hi experts,

I am asking for customer.

My customer wants to use F280036 CLB to realize CCSI communication. If CCSI communication over CLB, does this consume additional resources like SPI/PWM/ADC overrided? I checked the tlc698x_lp589x_f280039x demo code, seems like it needs to override EPWM&SPI&DMA resource. Could you help to confirm that?

Best Regards

F29H859TU-Q1: [F29H85x] Single-Image Boot Sequence for CPU1 and CPU3

ky pham — Wed, 23 Sep 2026 13:24:38 GMT

Part Number: F29H859TU-Q1

Currently, we are developing software for the F29H85x target.

As I understand, the TI SDK multicore example uses separate applications for CPU1 and CPU3. CPU1 boots first, releases CPU3 from reset, loads the CPU3 code to RAM, and configures the CPU3 reset vector.

However, our design uses one application image for both CPU1 and CPU3. After CPU1 releases CPU3 from reset, we expect CPU3 to start from the same application entry/reset vector as CPU1 and execute the same application code.

Is this architecture supported on F29H85x? If yes, could you provide an example or guidance on the required startup code, reset-vector configuration, and linker script to support this approach?

F29P589DM-Q1: How many UARTs are available in F29P580DM5PZS MCU?

Muppidi Satish Kumar — Wed, 23 Sep 2026 12:06:41 GMT

Part Number: F29P589DM-Q1
Other Parts Discussed in Thread: SYSCONFIG

Hi,

Regarding the part F29P580DM5PZS, when we look in the datasheet the availability of UARTs (Not LIN/SCI) count is mentioned as 4 in Table 4.1 (device comparison).

In Another table 5.3 Digital signals it is mentioned as 6 UARTs (UART_A to UART_F )

How many UARTS (other than LIN or SCI) are available in mentioned MCU?

F29H859TU-Q1: CPU3 run ADCA in multi-application

Jenney Ni — Wed, 23 Sep 2026 09:39:34 GMT

Part Number: F29H859TU-Q1

Hi all,

In a multi-core application where CPU1 runs MCAL and CPU2 runs the SDK, I moved ADCA, which was originally assigned to CPU1, to CPU3. I encountered the following issues:

Clock error due to a duplicate name: There was a clock naming conflict with the CPUTimer clock. After I renamed it, the error disappeared. Is this modification acceptable and safe?
Initialization location conflict: The tool indicates that all of this initialization code is executed on CPU1. Does this mean I am strictly required to initialize ADCA within CPU1? Can CPU3 directly use ADCA without performing any initialization?

Regards,

Jenney

F29H859TU-Q1: boot pin

Jenney Ni — Wed, 23 Sep 2026 08:59:16 GMT

Part Number: F29H859TU-Q1

Hi all,

During the MCU initial boot-up, the device checks the status of these two boot pins to determine the medium from which it will boot. If GPIO84 (PIN119) is later multiplexed as a PWM output, will this cause any issues?

On the hardware side, GPIO72 is directly shorted to 3.3V to pull it high, while the other GPIO is pulled high through a resistor. Does this design have any potential flaws?

Regards,

Jenney

TMS320F28374S: TMS320F28374S: TMS320F28374S: periodic STA/STL RAM diagnostics — CERRTHRES / FMEDA Diagnostic Used in Application, and STA_MARCH_COPY false-fail risk

Jason Su — Wed, 23 Sep 2026 07:19:38 GMT

Part Number: TMS320F28374S

Device: TMS320F28374S
Software: C2000 SafeTI Diagnostic Library / Self-Test Application (STA) v1.00.02.00
Use case: industrial, IEC 61508
Periodic calls (runtime / PEST):
STA_RAM_DETECT -> STL_RAM_detectError()
STA_MARCH_COPY -> STL_March_testRAMCopy() + STL_March_checkErrorStatus()

We recently received several field reports of periodic RAM diagnostic FAIL.
Below is how we call STA/STL at runtime; we have a few questions on usage,
pass/fail severity, FMEDA, and possible March false FAIL.

Periodic entry (application)

/* first */
sta_tests_testdevice_handle(STA_RAM_DETECT);
/* immediately after */
sta_tests_testdevice_handle(STA_MARCH_COPY);

A. STA_RAM_DETECT (Dummy Read / ECC-Parity observation)

Each STA_RAM_DETECT call dummy-reads one SRAM block (32-bit reads), then
rotates through the on-chip SRAM map.

Per SPRS881K Table 7-6:
ECC blocks: M0, D0, D1 -> SPRUI78C SRAM1 (6.3.9)
Parity blocks: LSx, GSx, MSGRAM -> SPRUI78C SRAM2 (6.3.10)
The Dummy Read itself is the method in SPRUI78C 6.3.3 (SRAM7).

Sectors in rotation (STA init):
M0, M1, D0, D1, LS0-LS5, GS0-GS11, CLA-to-CPU MSGRAM, CPU-to-CLA MSGRAM
Skipped after increment (same as March):
- M1 (stack)
- GS3 (STA variables / March copy buffer)
- CLA-to-CPU MSGRAM (CPU has no write access)

From sta_user.c (STA_User_initRAMErrDetectTest) + sta_tests.c:

STA_User_ramErrDetectObj.corrErrorThreshold = 1U;
STA_User_ramErrDetectObj.corrErrorIntVector = STA_Util_corrErrorISR_RAM;
STA_User_ramErrDetectObj.uncNMIVector       = STA_Util_uncorrErrorNMIISR_RAM;
STA_User_ramErrDetectObj.startAddress =
    STA_RAMTest_StartAddr[STA_User_ramErrDetect_Count];
STA_User_ramErrDetectObj.endAddress   =
    STA_RAMTest_EndAddr[STA_User_ramErrDetect_Count];
/* then advance STA_User_ramErrDetect_Count; skip indices for M1 / GS3 /
   CLA-to-CPU MSGRAM */

MemCfg_setTestMode(memSection, MEMCFG_TEST_FUNCTIONAL);

testStatus = STL_RAM_detectError(STA_User_ramErrDetectHandle);
if (STL_RAM_DETECT_PASS == testStatus)
{
    /* PASS */
}
else
{
    /* FAIL -> enter safe state */
}

From stl_ram.c STL_RAM_detectError() (Diag Lib v1.00.02.00), as we read it:

/* clear status / interrupt flags (also clears single-bit error count) */
HWREG(...CERRCLR)  = 0xFFFFFFFFU;
HWREG(...CEINTCLR) = ...;
HWREG(...UCERRCLR) = 0xFFFFFFFFU;

MemCfg_setCorrErrorThreshold(ramErrDetectHandle->corrErrorThreshold);

/* dummy-read 32 bits at a time from startAddress to endAddress */
for (address = start; address <= end; address += 2U)
    dummyRead = HWREG(address);

ramErrDetectHandle->corrErrorCount = MemCfg_getCorrErrorCount();
/* corrErrorCount is stored but not used for pass/fail */

if (((MemCfg_getUncorrErrorStatus() & MEMCFG_UCERR_CPUREAD) != 0U) ||
    ((MemCfg_getCorrErrorStatus()   & MEMCFG_CERR_CPUREAD)  != 0U))
    testStatus = STL_RAM_DETECT_FAIL;
else
    testStatus = STL_RAM_DETECT_PASS;

So (please confirm): a hardware-corrected 1-bit ECC data error still sets
CERRFLG / CPUREAD and returns FAIL; we do not use CERRCNT as the criterion.

We understand from the documents (please confirm):
- SPRUHX5H 3.11.1.7: a 1-bit error in one 16-bit ECC data word is corrected
and written back; address ECC, ECC double-bit, and all parity errors
are uncorrectable (UCERR / NMI). Parity memories have no correctable path.
- After correction, CERRFLG is still set and CERRCNT increments.
- SPRUHX5H 3.11.1.7.2: CERRTHRES controls when the correctable-error
interrupt is generated (if enabled), not whether a flag is set.
- SPRUHX5H 3.6.6: "A typical threshold setting to avoid triggering on
transient errors which are corrected, but identify persistent faults is 10."

B. STA_MARCH_COPY (non-destructive March13N) — our implementation

This follows Diag Lib UG v1.00.02.00 Section 5.15 and SPRACB9:
STL_March_testRAMCopy() copies the window, writes/reads the March patterns,
then restores the original contents.
STL_March_checkErrorStatus() then reads CERRFLG / UCERRFLG.

1) Periodic call order
STA_RAM_DETECT (first)
STA_MARCH_COPY (immediately after)

2) Sectors / window
Each call tests one window only:
length = 63 -> 64 x 32-bit = 128 x 16-bit
Address advances inside the current sector (AddrCnt); when the sector
end is reached, move to the next sector.

Tested:
M0, D0, D1,
LS0-LS5,
GS0-GS2, GS4-GS11,
CPU-to-CLA MSGRAM

Skipped:
M1 (stack)
GS3 (STA variables / copy buffer STA_User_ramTestGS3Data)
CLA-to-CPU MSGRAM (CPU cannot write)

3) Patterns on the same window (fixed order inside one call)
1. STL_MARCH_PATTERN_ONE -> STL_March_checkErrorStatus()
2. STL_MARCH_PATTERN_TWO -> check (CERR/UCERR cleared between patterns)
3. STL_MARCH_PATTERN_THREE -> check
4. STL_MARCH_PATTERN_FOUR -> check
Any non-PASS check is ORed into FAIL.

4) Source — init (sta_user.c STA_User_initMarch), simplified:



uint32_t addrInterval =
sizeof(STA_User_ramTestGS3Data) / sizeof(uint16_t); /* 128 x 16-bit */

STA_User_marchErrorObj.address =
STA_RAMTest_Addr[STA_User_RamMarchCopy_Count]
+ STA_User_RamMarchCopy_AddrCnt * addrInterval;
STA_User_marchErrorObj.ramSection =
STA_RAMTest_Sect[STA_User_RamMarchCopy_Count];
STA_User_marchErrorObj.xorMask = 0x00000000U;
STA_User_marchErrorObj.testMode = MEMCFG_TEST_FUNCTIONAL;
/* then advance AddrCnt / sector count; skip M1, GS3, CLA-to-CPU MSGRAM */

5) Source — body (sta_tests.c case STA_MARCH_COPY), simplified:

MemCfg_clearUncorrErrorStatus(MEMCFG_CERR_CPUREAD |
                              MEMCFG_CERR_DMAREAD |
                              MEMCFG_CERR_CLA1READ);
MemCfg_clearCorrErrorStatus(MEMCFG_CERR_CPUREAD |
                            MEMCFG_CERR_DMAREAD |
                            MEMCFG_CERR_CLA1READ);

STA_User_initMarch();
Setup_March_Interrupt();

/* pattern ONE (TWO / THREE / FOUR are the same; clear CERR/UCERR between) */
STL_March_testRAMCopy(STL_MARCH_PATTERN_ONE,
                      STA_User_marchErrorObj.address,
                      63U, (uint32_t)STA_User_ramTestGS3Data);
returnVal |= STL_March_checkErrorStatus();
/* then PATTERN_TWO / THREE / FOUR the same way */

STA_Tests_testDevice() runs from Flash (not from the RAM under test).
The copy buffer is in GS3, which is excluded from the DUT.
We do not halt CLA or DMA around this March window during PEST.

Questions

Q1. Intended use
For periodic (PEST) RAM diagnostics on F28374S, is the combination below
the intended STA/STL usage? (SPRUI78C 6.3.3 / 6.3.9 / 6.3.10 / 6.3.12;
Diag Lib UG 5.15)
STA_RAM_DETECT -> SRAM1 / SRAM2 observation, and/or SRAM7 data scrubbing
STA_MARCH_COPY -> SRAM3 software test of SRAM (non-destructive March13N)
Is anything missing or incorrectly applied in the code above?

Q2. Correctable vs uncorrectable in STL_RAM_detectError()
The API returns FAIL for both correctable and uncorrectable flags.
For ECC memories (M0 / D0 / D1), may the application tolerate a bounded
number of correctable errors (hardware already corrected and wrote back)
and only enter the safe state on uncorrectable errors, or after the
correctable count reaches a threshold?
We understand this does not apply to parity memories (LSx / GSx / MSGRAM),
where every error is uncorrectable.

Q3. Role of corrErrorThreshold = 1
Does corrErrorThreshold / CERRTHRES only control the correctable-error
interrupt (SPRUHX5H 3.11.1.7.2), and not the return value of
STL_RAM_detectError()?
In other words: changing 1 -> 10 would change interrupt timing only,
and the API would still FAIL on the first CERRFLG?

Q4. FMEDA / threshold = 10
If we react only when CERRCNT >= 10 on ECC memories:
a) Is that the intended use of the typical value in SPRUHX5H 3.6.6?
b) Does TI recommend 10 for industrial / IEC 61508, or another value?
c) Versus treating every CERRFLG as FAIL, do the FMEDA
"Diagnostic Used in Application" settings need to change?
Our current FMEDA "Diagnostic Used in Application" settings for RAM System:
SRAM1 SRAM ECC = 1
SRAM2 SRAM Parity = 1
SRAM3 Software Test of SRAM = 0
SRAM7 Data scrubbing = 0
If we change the application reaction for correctable ECC to a
count-based threshold, do these Diagnostic Used in Application
values need to change (especially SRAM1 / SRAM7)?

Q5. STA_MARCH_COPY false-fail risk
Given the sector list, pattern order, and source above:
- STA wrapper in Flash
- M1 / GS3 / CLA-to-CPU MSGRAM skipped
- copy buffer in GS3
- CLA / DMA not halted during the March window
Can STL_March_testRAMCopy() still produce a false FAIL by writing /
restoring diagnostic state, or if CLA / DMA / an ISR accesses the same
window during the test?
Which additional regions or concurrent-access constraints does TI
require for PEST use of STL_March_testRAMCopy()?

We appreciate your guidance on the intended use, FMEDA Diagnostic Used in
Application settings, and whether our March implementation can false-fail.
We would rather keep the diagnostics as specified than invent a looser
pass/fail rule.

TMS320F28P659DK-Q1: Clarification on CPU1 and CPU2 HWBIST Support for F28P659DK8PZPQ1

Sang-il Nam — Wed, 23 Sep 2026 01:56:29 GMT

Part Number: TMS320F28P659DK-Q1

Hello,

I am evaluating the F28P659DK8PZPQ1 device, which supports lockstep operation on CPU2.

The F28P65x datasheet lists the following features:

* Lockstep on C28x CPU2
* HWBIST on non-lockstep devices

Based on the phrase “HWBIST on non-lockstep devices,” it appears that HWBIST may not be supported on F28P65x devices equipped with CPU2 lockstep.

However, the F28P65x Technical Reference Manual contains descriptions and register information related to both CPU1 HWBIST and CPU2 HWBIST. Therefore, I would appreciate clarification regarding the exact device-specific implementation for F28P659DK8PZPQ1.

Could you please confirm the following?

1. Is HWBIST for CPU1 supported on the F28P659DK8PZPQ1?

2. Is HWBIST for CPU2 supported on this device, or is it replaced entirely by the CPU2 lockstep comparator?

3. Does the datasheet statement “HWBIST on non-lockstep devices” mean that neither CPU1 nor CPU2 HWBIST is available on any F28P65x lockstep device?

4. If the HWBIST registers are described in the family TRM but HWBIST is not supported on this particular device, are those registers simply part of the common family-level register description and unavailable or nonfunctional on the F28P659DK8PZPQ1?

5. Can CPU2 lockstep operation be disabled temporarily to perform CPU2 HWBIST, or is this configuration not supported?

6. If HWBIST is unavailable for CPU1 as well, what diagnostic mechanism does TI recommend for detecting permanent or latent faults in the CPU1 logic on this device?

7. Is there a device-specific table, safety manual section, or other document that explicitly confirms the availability of CPU1 and CPU2 HWBIST for each F28P65x device variant?

For comparison, I understand that a non-lockstep device such as the F28P650DK6PZP supports HWBIST, whereas the F28P659DK8PZPQ1 uses CPU2 lockstep. I would like to confirm whether selecting the lockstep device results in HWBIST being unavailable for both CPUs, rather than only for CPU2.

Thank you for your assistance.

Best regards,
Sang-il

F29P329SM-Q1: LPOST check function SSU configuration in SE device

Shuqing Zhou — Tue, 22 Sep 2026 15:39:14 GMT

Part Number: F29P329SM-Q1

Hi team,

Regrading this issue:https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1683960/f29p329sm-q1-how-to-run-the-lpost-in-se-device/6491117

could you help to check is it any requirement for the lpost_check function ssu configuration in SE device? for example, is lpost_check function must in LINK2 or LINK1 or any other LINK is ok? I ask this because customer will let device run in SSUMODE2

BRs

Shuqing

TMS320F280039-Q1: GPIO Ptotection

Shri Ram — Tue, 22 Sep 2026 09:22:31 GMT

Part Number: TMS320F280039-Q1

Hi Team,

We are using TMS320F280039-Q1 as a controller for housekeeping operations. We have folling doubt.

Do we have to provide overvoltage protection for GPIO and ADC pins, or is it already provided inside the chip?

If it is not provided, please suggest how to protect those pins from overvoltage, reverse voltage, and over current.

Regards,

Shri

F29P329SM-Q1: Does F29P329SM1QPZSRQ1 have Lockstep though it is single core MCU?

Muppidi Satish Kumar — Tue, 22 Sep 2026 08:41:52 GMT

Part Number: F29P329SM-Q1

Hello,

F29P329SM1QPZSRQ1 is single (C29x) MCU. According to the product identification, it is enabled for fixed lockstep. Does this mean, internally it have another core dedicated for only lockstep? What is the RAM size for this? Any differences in peripherals availability when compared to F29P58x? I am not able to distinguish this part from F29x regular TRM. Please share any documentation available for this part?

LAUNCHXL-F28P55X: XTAL cfg sequence for LAUNCHXL-F28P55X?

AnBer — Mon, 21 Sep 2026 22:04:50 GMT

Part Number: LAUNCHXL-F28P55X
Other Parts Discussed in Thread: C2000WARE

Team,

LAUNCHXL-F28P55X (populated with REVID 02) has Y2 (16Mhz crystal) populated on GPIO18/GPIO19:

On CCS 21 I have imported the C2000Ware_26_01_00_00 empty_driverlib_project for the LAUNCHXL-F28P55X
from C:\ti\c2000\C2000Ware_26_01_00_00\driverlib\f28p55x\examples\empty_projects

In C2000.sycfg I made sure I have the according config:

-How is the CLK config happening on the SW side?

CLK config does not seem to hapen in syscfg
but it seems to be done in device.h (comimg from C:\ti\c2000\C2000Ware_26_01_00_00\device_support\f28p55x\common\include) has at line 281:
// 20MHz XTAL on controlCARD is used as the PLL source.
// For use with SysCtl_getClock().
//
#define DEVICE_OSCSRC_FREQ 20000000U

However I do not find in this file any reference to actual crystal of the the LAUNCHXL-F28P55X.

Could you clarify what is the SW portion that does the LAUNCHXL-F28P55X specific CLK config to use the external XTAL?

Thanks in advance,

Anber

TMS320F28377D-Q1: Errata: VREG: VREG Will be Enabled During Power Up Irrespective of VREGENZ

HS FAE Germany — Mon, 21 Sep 2026 13:57:58 GMT

Part Number: TMS320F28377D-Q1

Hi,
if the VREG is switch on due to errata "VREG: VREG Will be Enabled During Power Up Irrespective of VREGENZ"?
How long is it switch on or after how many ms will it be swiched off again?

Regards, Holger

TMS320F28035-EP: Assign absolute address to table using linker cmd file

Gregory Helton — Mon, 21 Sep 2026 13:11:00 GMT

Part Number: TMS320F28035-EP
Other Parts Discussed in Thread: TMS320F28035

I am trying to assign an absolute address to a table using the linker command file for a TMS320F28035.

The memory region is called APP_CODE, and is defined within the MEMORY region as part of a group that requires a CRC. The table (cal_table) will go into a section within this memory region.

MEMORY
{

GROUP
{
RTS_LIB : origin = 0x3EA000, length = 0x0C00, FILL = 0xFFFF
MAIN_LOC : origin = 0x3EAC00, length = 0x0300, FILL = 0xFFFF
APP_CODE : origin = 0x3EAF00, length = 0xB0DF, FILL = 0xFFFF
FW_REV : origin = 0x3F5FDF, length = 0x0001, FILL = 0xFFFF
} crc( _crc_table, algorithm=CRC32_PRIME )

//more stuff

}

A section needs to be created called .cal_table. This section is created WITHIN the APP_CODE memory region at an absolute address of 0x3F2000

SECTIONS
{

// more stuff

.cal_table:
{
*(.cal_table_section)
} > APP_CODE ORIGIN = 0x3F2000

// more stuff

}

The calibration table is linked into the .cal_table_section with a pragma as follows.

#pragma DATA_SECTION(iMagCalTable, ".cal_table_section")
//__attribute__((section(".cal_table_section")));
int16_t const iMagCalTable[IDX_3600]=
{
3000,
3005,
3009,
3014,

// etc

}

All of this is from examples that I have found, but NONE of them work as expected.

Here is the error message.

error #10026-D: expecting output section, GROUP, or UNION instead of "="

It appears as if the linker does not like the absolute address assignment.

The .cal_table_section is a section within the APP_CODE memory region. The ._cal_table_section resides at the end of the APP_CODE memory region - hence the absolute address memory assignment.

Does anyone have any ideals to accomplish this ?

F29H850DM: LFU example

HS FAE Germany — Mon, 21 Sep 2026 12:57:25 GMT

Part Number: F29H850DM

Hi,
is there an example for live FW update?

Regards, Holger

F29H850TU: freertos_amp_cpu1_cpu3_multi_c29x1 does not work

Hang Yang — Mon, 21 Sep 2026 10:16:07 GMT

Part Number: F29H850TU

Hi Experts,

I can not run example freertos_amp_cpu1_cpu3_multi_c29x1

It goes to NMI after running the CPU1

The reproduction is simple, load CPU1.out and click resume twice.

Regards,

Hang

F29P329SM-Q1: How to run the LPOST in SE device

Shuqing Zhou — Mon, 21 Sep 2026 09:57:14 GMT

Part Number: F29P329SM-Q1
Other Parts Discussed in Thread: SYSCONFIG

Hi team,

I ask this for my customer. My customer run the device in HS-SE status, and want to run LPOST

I have already changed the device to SE device, and modify the sysconfig to enable the LPOST and MPOST and program the SECCFG to the device

but after running the lpost_check function, the device will run into NMI

after checking the HSM userguide, i find the LPOST register belongs to HSM by default

and if i check the LPOST register in HSM side, it shows LPOST is enabled and LPOST test pass

customer needs to do the LPOST in c29 side, could you help to give a demo to realize the LPOST and MPOST in HS-SE device?

What's more, is it any requirement for the lpost_check function ssu configuration? for example, is lpost_check function must in LINK2 or LINK1 or any other LINK is ok? I ask this because customer will let device run in SSUMODE2

BRs

Shuqing

AM2612: How to get current time of ICSS_TimeSync in Industrial Communication SDK

Yelena Mao — Mon, 21 Sep 2026 08:40:24 GMT

Part Number: AM2612

Time Sync function is working in the ethernetip_adapter example. And the time is synchronized to the Grand Master Clock.

There is one API “TimeSync_getCurrentTime()” provided by ICSS TimeSync. Its input parameter “timeSyncParamsHandle” is initialized by the TI library “ethernetip_adapter_mii_icss_fwhal.am261x.r5f.ti-arm-clang.release.lib”.

Question1: To get the current time using this API, I should provide the input parameter ”timeSyncParamsHandle”. How can I get the “timeSyncParamsHandle”?

The “cipSyncConfig_t” is a data structure defined based on the CIP Sync Instance Attributes. I want to get the Instance Attribute 3 value “System Time Microseconds”. However, I got the value of 0 using the API “EI_API_CIP_getAttr_lint()”.

Question2: Can I use this API to get the Time Sync Object Instance Attribute 3 (System Time Microseconds)?

Question3: the timeSyncHandle and cipSyncObj are provided by “EIP_Handle”. How can I access this handler? It is initialized and configured by the TI library “ethernetip_adapter_mii_icss_fwhal.am261x.r5f.ti-arm-clang.release.lib”.

AM625: AM62x M4F: very slow access to shared memory at 0x70000000 (~110 ns/word?) – is my configuration wrong or is this expected?

Soheil jbbr — Sun, 20 Sep 2026 14:50:06 GMT

Part Number: AM625
Other Parts Discussed in Thread: SYSCONFIG

Hello,

Setup

Device: AM62x (ALW), MCU+ SDK 09.00.00, core m4fss0-0, NORTOS
The M4F runs a 312 µs periodic timer ISR (MCU_DMTIMER1) that does real-time power-system processing (ADE9000 data, FFT, symmetrical components).
The M4F exchanges data with the A53 (Linux) through a shared block placed in OCSRAM at 0x70000000.

Linker configuration

USER_SHM_MEM : ORIGIN = 0x70000000, LENGTH = 0x10000

.user_shared_mem (NOLOAD) : { *(.user_shared_mem) } palign(8) > USER_SHM_MEM

volatile ade9000_cores_pure_values_t gAdeSharedValues
    __attribute__((section(".user_shared_mem"), aligned(128)));       // 988 bytes
volatile ade9000_instantaneous_cores_pure_values_t gAdeInstantValues
    __attribute__((section(".user_shared_mem"), aligned(128)));       // 16,384 bytes
volatile whole_data_t gWholeData
    __attribute__((section(".user_shared_mem"), aligned(128)));       // 6,748 bytes (packed struct)

SysConfig (MPU / address translation)

CONFIG_MPU_REGION0: default, Device, no execute
CONFIG_MPU_REGION1: base 0x0, size 18
CONFIG_MPU_REGION2: base 0x70000000, size 28, attributes NonCached
ATR region 7: local 0x70000000 → system 0x70000000, size 28

What the ISR does

memcpy(&ade_instantaneous_local_values, ade_instantaneous_shared_values, 16384); // shared -> local (DRAM)
memcpy(&ade_local_values, ade_shared_values, 988);                               // shared -> local
/* ... processing on local copies ... */
memcpy(sh_data, &local_data, 6748);                                              // local -> shared

Total per ISR: ~17.4 KB read from and ~6.7 KB written to 0x70000000.

Problem
Accessing the shared memory takes about 665 µs per ISR (measured with ClockP_getTimeUsec() and a GPIO toggle), which is more than twice my 312 µs period. That works out to roughly 110 ns per 32-bit access. [Benchmark results: DWT cycle count for reading 1024 words from local DRAM 0x30000: ___ cycles; from OCSRAM 0x70000000: ___ cycles; from DDR 0x9CC00000: ___ cycles]. Moving the shared data to DDR is even slower, so it is not an option.

Questions

Is ~100+ ns per single-word read/write from the M4F to OCSRAM (0x70000000) expected on AM62x? What is the typical/worst-case latency of the M4F → MAIN domain path (OCSRAM and DDR)?
Is my MPU/ATR configuration correct for this region (Normal non-cacheable, ATR 1:1)? Could a different attribute (e.g. Device vs. Normal) or different ATR settings improve throughput? I also noticed that the base 0x70000000 is not aligned to the 512 MB size of REGION2 and plan to change it to 64 KB.
Is there a way to get burst transfers from the M4F to main-domain memory (e.g. LDM/STM behavior, write buffering), or is DMA (BCDMA/UDMA block copy) the recommended way to move larger blocks?
What is TI's recommended pattern for sharing data between the M4F and the A53 when the M4F has a hard real-time deadline? For example, is it valid to place the shared block in the M4F's own DRAM and let the A53 access it through the M4FSS DRAM window?

I want to confirm that the raw latency is expected and that my configuration is not making it worse.

Thank you!

F29H850TU: Syncing ePWM with XCMP in 3-phase applications

Hang Yang — Sun, 20 Sep 2026 10:50:56 GMT

Part Number: F29H850TU

Hi Expertcs,

From the related thread we know ePWM with XCMP enabled do not take the sync-in input.

In this case, how can customer achieve the sychronization of a 3-phase varying frequency control scheme?

Customer tried syncing the ePWM at the beginning, but the phase would drift as time went by.

Regards,

Hang

F29H850TU: Syncing ePWM with XCMP functions

Hang Yang — Sun, 20 Sep 2026 10:50:00 GMT

Part Number: F29H850TU

Hi Expertcs,

From the related thread we know ePWM with XCMP enabled do not take the sync-in input.

In this case, how can customer achieve the sychronization of a 3-phase varying frequency control scheme?

Customer tried syncing the ePWM at the beginning, but the phase would drift as time went by.

Regards,

Hang

LAUNCHXL-F28P65X: Unable to enable Lockstep module

Muppidi Satish Kumar — Sat, 19 Sep 2026 03:38:13 GMT

Part Number: LAUNCHXL-F28P65X
Other Parts Discussed in Thread: C2000WARE

Hello,

I would like to enable Lockstep module (ofcourse compare enable) on Launchpad F28P65x. I referred Technical reference manual (https://dev.ti.com/tirex/explore/node?isTheia=false&node=A__AMkAGl.8suzL8XPB0e3brQ__c2000ware_devices_package__coGQ502__LATEST) Lockstep Compare Module sectionand followed as per the TRM

My code implementation is

After calling "vEnableLcm()" function, I called "u8IsLcmLock()" to see whether LCM module enabled or not. Unfortunately, this function returns 0 (not enabled). I am not checking with debug connection. I used printf() to see the status.

Please help me to correct it.

F29H850DM: Does TI provides functional safety collateral?

Muppidi Satish Kumar — Sat, 19 Sep 2026 02:31:33 GMT

Part Number: F29H850DM

Hello,

We are referring F28x and F29x MCU's for our functional safety industrial application. When I referred C2000 academy page, I found some Functional safety collateral for F28x (F28P65x) MCU. There is no such mentioning in F29x section other than SSU and HSM. Does F29x have functional safety features and Collateral? Which one you recommend us for our functional safety (say SIL3) among F28x and F29x MCUs?

Reason for looking into F29x MCU's:

Architectual changes, mainly on RAM structure which is simple when compared to F28x
Byte addressable, which makes my application porting (from Cortex-M to C29x) easier.

F29H859TU-Q1: How the compiler implements trigonometric functions

Kien — Fri, 18 Sep 2026 14:12:02 GMT

Part Number: F29H859TU-Q1

Hi Champs,

When using the C29x with FPU/TMU64 and -ffast-math enabled, my customer observed approximately 3x improvement in execution performance, with a corresponding reduction in CPU load compared with the configuration in which these options are disabled.

Could you please clarify how the compiler implements trigonometric functions such as sinf() and cosf() in the following configurations?

FPU/TMU64 and -ffast-math enabled
FPU/TMU64 enabled but -ffast-math disabled
FPU/TMU64 disabled

In particular, they would like to understand whether these functions are implemented using TMU instructions, compiler intrinsics, inline approximations, or runtime library calls in each configuration.

Regards,

Kien