C2000 microcontrollers forum - Recent Threads

TMS320F280039: I2C SCL Line Stuck Low and Stop Condition Not Triggering

Ardavan Pourkeramati — Fri, 05 Jun 2026 18:54:54 GMT

Hello,

I have written an I2C driver based on i2c_ex2_eeprom.c, and I am facing an issue with the SCL line becoming stuck low. This is an intermittent issue occurs somewhat randomly.

When this occurs, I notice the final message before faulting is correct (using logic analyzer), except that the stop condition does not occur.

I believe this is similar to the issue found here: https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1447879/tms320f280048c-q1-i2c-not-able-to-generate-stop-condition

Was this issue ever resolved internally? Thank you in advance.

TMS320F280039C-Q1: can registers

Jenney Ni — Fri, 05 Jun 2026 11:57:39 GMT

Part Number: TMS320F280039C-Q1

Hi all,

The customer is experiencing software anomalies under high-temperature conditions. The CAN module's software logic is suspected. The following questions need to be checked:

1. In the customer's software logic, it is required to continuously wait for the Busy flag in the CAN_IFxCMD register to be cleared. Therefore, is there any operating condition under which the Busy bit in CAN_IF1CMD and CAN_IF2CMD registers remains set to 1 for more than 1ms?
2. Could external pin voltage levels, ambient temperature, or the operating condition of the CAN transceiver affect the Busy bit staying continuously set to 1? My understanding is that the Busy bit in CAN_IF1CMD and CAN_IF2CMD registers reflects an internal MCU data transfer status and is unrelated to external peripherals — is this correct?
3. Under what operating conditions would the Timer module's overflow flag fail to be set to 1? (The MCU crystal oscillator has been verified as normal, and PWM output is also normal.)

Regards,

Jenney

AM13E23019: How MCU handle the interrupt with the same priority

Joe Ji — Fri, 05 Jun 2026 10:33:03 GMT

Part Number: AM13E23019

Hi Expert

Could you please share the AM13E23019 SPI timming spec? there is no details in datasheet, customer need to test in their pilot run demo.

Thanks

Joe

AM13E23019: How MCU handle the interrupt with the same priority

Joe Ji — Fri, 05 Jun 2026 10:30:22 GMT

Part Number: AM13E23019
Other Parts Discussed in Thread: SYSCONFIG

Hi Expert

There are 2 questions:

#1 is interrupt round-robin rule

Want to ask the Interrupt use case: there are 3 interrupts: PWM INT1/ SPI INT2/ Timer INT3.

INT1 and INT2 set to the same priority1, and INT3 set to the lower priority2.

There is a case:

1.CPU is running INT3,

2.INT1 and INT2 come at the same time

3.INT1 comes again following "2"

According to TRM CPU->Interrupt section, when "2" happens, CPU will store INT3 in stack and serve INT1 and INT2 this process is controlled by NVIC.

The question is when "2" ends and CPU runs INT3 again and "3" happens, will INT1 can interrupt INT3 again, or it need to wait for INT3 finish?

#2 is what is Default Interrupt Priority in sysconfig? there is no details in TRM, is it something in CMSIS?

Thanks

Joe

TMS320F28P650DH: Can only configure ESC port0 GPIO without configure Port1 gpio?

Zane Wei — Fri, 05 Jun 2026 09:47:49 GMT

Part Number: TMS320F28P650DH

Hi Team,

My customer only need to use ESC port0, and want to Port1 GPIO to control other peripheral. But my customer found it they don't configure Port1 GPIO to ESC function. The master can't scan this device.

So it need to be configure port0 and port1 at the same time, even if don't use port1.

Best Regards,

Zane

TMS320F28377D: Question regarding integer overflow and literal typing in TI E2E thread #1644136

Sang-il Nam — Fri, 05 Jun 2026 07:20:25 GMT

Part Number: TMS320F28377D

Hi,

While browsing the community, I came across the thread linked below and had a few technical questions regarding the TI engineer's response.

Thread URL: https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1644136/tms320f28p650dk-the-program-for-tms320f28p650dk

In the original post, the author provided the following constant definition and code snippet:

#define CURRENT_SAMPLE_DEFAULT_OFFSET_MAX 39321 // 32768 * 1.2
volatile int32_t temp2;
temp2 = CURRENT_SAMPLE_DEFAULT_OFFSET_MAX; // temp2 = 2457

I read the TI engineer's explanation regarding this, but I am somewhat confused by it.

On a TMS320F28x MCU, even if we define the macro as a bare decimal literal and assign it to a 32-bit variable like above, the value 39321 is successfully and correctly stored in temp2. According to the C standard specifications, the type of an unsuffixed decimal integer literal is automatically determined as the first type in the sequence of int → long int → long long int that can fully represent its value. Since 39321 exceeds the maximum value of a signed 16-bit int (32767), it should inherently be treated as a 32-bit long int.

Even if the value 39321 were processed as a 16-bit type and truncation occurred, the result would still not be 2457. (Of course, if the value is assigned to a 12-bit register, 0x9999 would be truncated to 0x0999, which explains where the value 2457 comes from.)

If we perform compile-time arithmetic operations that overflow 16-bit limits without explicit casting, truncation due to overflow will occur as shown in the examples below. However, even in those cases, the TI compiler alerts the user during the build process with a specific warning message:

#define TEST1 (30000 * 30000)
#define TEST2 (0x4120 << 8)

volatile int32_t temp1, temp2;

temp1 = TEST1; // temp1 = -5888 (Truncated)
temp2 = TEST2; // temp2 = 8192  (Truncated)

[Compiler Warning]
"xxx.c", line nnn: warning #62-D: integer operation result is out of range

(While it is true that attaching suffixes like L or UL when defining constants is the correct method and good habit to prevent truncation phenomena like the example) Given this compiler behavior and the C standard rules for literal promotion, is the explanation provided in the original TI response entirely accurate? Or am I missing some C2000-specific compiler behavior here?

I would appreciate any further clarification on this matter.

Best regards,
Sang-il

TMS320F28388D: SPLL_3Ph_SRF loop Coefficients calculations

Nikileshwar Vamanaguntla — Fri, 05 Jun 2026 07:14:42 GMT

Part Number: TMS320F28388D
Other Parts Discussed in Thread: C2000WARE

Hi Team,

Iam using TMS320F28388D for my application. In this Iam Using the SPLL_3ph_SRF fuction in which i trying to find the loop coefficients for my apllications. but Iam not able to find the Correct calculation procedure for the same. Please guide me to find them

for reference: loop coefficients iam taking about are,

TINV_spll_3ph_2.lpf_coeff.b0 = 166.9469f; // SPLL filter parameter based on SPLL guide

TINV_spll_3ph_2.lpf_coeff.b1 = -166.25305f; // SPLL filter parameter based on SPLL guide

Thanks in advance,

Nikileshwar Vamanaguntla

TMS320F28377D: How long over/ below MAX/Min voltage will cause device damage?

Zane Wei — Fri, 05 Jun 2026 07:03:13 GMT

Part Number: TMS320F28377D

Hi Team,

My customer is using F28377, but in the hardware test, they found eCAP IO maybe over 3.7V(778ps), and below -0.3V(1.1ns). Customer want to know it will damage device?

From my knowlege, I think damage device should have two condition, one is over voltage, another is energy.

Best Regards,

Zane

TMS320F28377S: Default State of GPIO pin upon 1st Power up

Prahaladh S — Fri, 05 Jun 2026 05:35:11 GMT

Part Number: TMS320F28377S
Other Parts Discussed in Thread: TPS2640

Hi,

We're planning to use TMS320F28377S in our application.

We want to understand the default state of GPIO pin upon 1st power up of the MCU (no code present inside the MCU & MCU not programmed).

We have connected one GPIO from MCU to TPS2640's SHDN pin directly without any pullup to supply. Want to understand the behaviour of the TPS2640 IC when the MCU powers up for the very 1st time.

Kindly guide us in this regard.

Warm Regards,

Prahaladh S

TMS320F28P650SK: Total output current of PWM channel

Colin Chen — Fri, 05 Jun 2026 03:08:42 GMT

Part Number: TMS320F28P650SK

Dear Expert,

We would like to know the total driving current of all output PWM channels of F28P650SK6. Currently, we only see that the maximum output current for a single channel is 20mA. We need 18 PWM outputs to directly drive the optocoupler at the backend, and the required driving current for a single channel is about 10mA. If it is turned on at the same time, is there any risk? Thank you

TMS320F28335: Intermittent CAN Communication Drop (Auto Recovery) Between TMS320F28335 DSP and Two Spartan 6 FPGAs

albert qiu — Fri, 05 Jun 2026 02:13:48 GMT

Part Number: TMS320F28335

I’m troubleshooting an intermittent, self-recovering CAN communication dropout on a field-deployed system with TMS320F28335 DSP (Rev 0/A) and two Xilinx Spartan 6 FPGAs. The failure points strongly to a known TI eCAN silicon errata, and I’m looking for workarounds and experience sharing. System details and symptoms are below. 1. System CAN Configuration & Communication Logic The F28335 eCAN runs in polling mode with four dedicated mailboxes for dual-FPGA independent CAN links: - Mailbox 1 (TX) / Mailbox 2 (RX): Communication between DSP and FPGA1 - Mailbox 3 (TX) / Mailbox 4 (RX): Communication between DSP and FPGA2 Normal operation: The DSP periodically transmits an incrementing heartbeat signal via TX mailboxes. Each FPGA replies automatically upon receiving valid DSP CAN frames, and the DSP receives responses via the corresponding RX mailboxes. Both TX/RX functions implement timeout protection to prevent program hanging. To prevent program deadlock, we have addedtimeout exit mechanisms in both DSP CAN transmit and receive functions to ensure program robustness. 2. Field Failure Phenomenon In field operation, CAN communication drops intermittently and recovers automatically. Outage time varies randomly from several seconds to tens of seconds. Key log evidence: Both FPGAs monitor the DSP heartbeat counter. During every fault event, the DSP heartbeat freezes simultaneously on both FPGAs at the same timestamp, with no errors logged on either FPGA side. 3. Root Cause Analysis & Suspicion Synchronous heartbeat stall on two independent FPGA nodes rules out FPGA, bus, transceiver, and power issues. The fault source is confirmed to be the F28335 DSP. Checking TI official errata: TMS320F28335 Rev 0/A silicon has a known eCAN transmit bug — CAN transmission may stop unexpectedly under certain conditions, while CAN reception remains normal. This matches our fault behavior perfectly: When DSP CAN TX fails, it stops sending heartbeat frames to both FPGAs. Without valid DSP frames, FPGAs do not send reply packets, causing full communication outage. The link auto-recovers because the TX fault is temporary and non-latched. 4. Questions & Expectations 1. Has anyone encountered this intermittent eCAN TX stall on F28335 Rev 0/A in polling-based multi-node CAN systems? 2. Are there proven software workarounds (e.g., error state polling, mailbox/module reset, re-init) to avoid this bug without hardware revision upgrade? 3. What are the typical trigger conditions for this eCAN TX errata? We need to reproduce it for lab verification. Thanks in advance for any feedback and suggestions!

Additionally, an external ADM706 hardware watchdog is added to the F28335. When the DSP detects a receive anomaly, it stops feeding the watchdog after 15 cycles, triggering a reset after 1.6 seconds. However, our fault data shows that even after a reset, CAN communication does not recover immediately.

TMS320F28P559SJ-Q1: How to trip PWM via DCC fault

Steve Lim — Fri, 05 Jun 2026 01:36:31 GMT

Part Number: TMS320F28P559SJ-Q1

Hi Champs,

Is there a way to directly trip the PWM when a DCC fault interrupt occurs, without any S/W intervention? I could not find the DCC fault as a source in the ePWM X-BAR.

Thanks,
Steve

TMS320F28P559SJ-Q1: How to trip PWM via DCC fault

Steve Lim — Fri, 05 Jun 2026 01:29:14 GMT

Part Number: TMS320F28P559SJ-Q1

Hi Champs,

Is there a way to directly trip the PWM when a DCC fault interrupt occurs, without any S/W intervention? I could not find the DCC fault as a source in the ePWM X-BAR.

Thanks,
Steve

F29P329SM-Q1: What's the alignment requirement for the variable in memory?

Shuqing Zhou — Thu, 04 Jun 2026 15:02:52 GMT

Part Number: F29P329SM-Q1
Other Parts Discussed in Thread: SYSCONFIG

Hi team,

I ask this for my customer.

My customer want to know if it any alignmnent requirement for the variable in the f29 memory

In sysconfig, it shows the flash sections should be 8 bytes aligned

In datasheet, it shows it should be 16 bytes aligned.

we are confused about this, could you help to explain it?

BRs

Shuqing

TMS320F2800137: [LAUNCHXL F2800137] Migration from F28379D: Code portability and peripheral register compatibility on CCS

Delta Nmur — Thu, 04 Jun 2026 13:39:16 GMT

Part Number: TMS320F2800137
Other Parts Discussed in Thread: LAUNCHXL-F28379D, LAUNCHXL-F2800137

Hi TI team,

I have some basic experience with the LAUNCHXL-F28379D (GPIO, ePWM, ADC, Interrupts, and simple PMSM control projects in CCS).

Now I need to migrate to the LAUNCHXL-F2800137 for PMSM motor control.

From a software development perspective, what are the main differences I should expect when moving from F28379D to F2800137?

Specifically:

How similar are the DriverLib APIs and CCS project structure?
Are there any major differences in interrupt, ADC, ePWM, or motor-control related peripherals?
Can most PMSM control code (FOC/SVPWM, ADC ISR, control loops) be reused with only peripheral configuration changes?
What are the most common issues engineers face when migrating from F28379D to F2800137?

I am mainly interested in software migration effort rather than hardware differences.

Thank you.

TMS320F28P550SJ: F28P55 USB boot mode usage

agostino facotti — Thu, 04 Jun 2026 13:33:55 GMT

Part Number: TMS320F28P550SJ
Other Parts Discussed in Thread: C2000WARE

Goodmorning,

I'm investigating the use of USB boot mode for F28P55 microcontroller;

in the Reference Manual it is stated that it should be available some tools to program the microcontroller using USB boot mode, but I didn't find any of those on the official TI page.

Is there any tool or example tool to program a F28P55 using internal USB boot mode?

Thanks!

TMS320F28P551SG: How to make sure the FSI communication waveform is correct or not?

GaryC — Thu, 04 Jun 2026 02:12:18 GMT

Part Number: TMS320F28P551SG

May I know how to make sure the FSI communication waveform is correct or not?

Below shows the I2C example. Could you share the similar example to me? Thanks

BR,

Gary

F29H850TU: M/P Product launch schedule.

Wilson Liang2 — Thu, 04 Jun 2026 02:08:28 GMT

Part Number: F29H850TU

Hi Sir

Could you please tell me the M/P product launch timeline for the F29H850? I need product design verification and pricing information. Thank you.

TMS320F28375D: Can not clear RESC register

Mehran Motallebi — Wed, 03 Jun 2026 18:26:02 GMT

Part Number: TMS320F28375D
Other Parts Discussed in Thread: C2000WARE

Hi,

I am using the "TMS320F28375D" MC. After power up I would like to clear the POR & XRSn bits of the "RESC" registre but for some reason they don't clear. Based on the chip's datasheet (Literature Number: SPRUHM8K (DECEMBER 2013 – REVISED MAY 2024) under the following section on page 397, I should be able to clear these bits after power up but I can't get them cleared.

RESC Register (Offset = 80h) [Reset = 00000003h]

I tried the following two approches and in both attemps the value stored in "resetSource" variable after clear attemp is equal to 3 (11b). Please advise.

resetSource = SysCtl_getResetCause();
SysCtl_clearResetCause(resetSource);
resetSource = SysCtl_getResetCause();
2)
resetSource = SysCtl_getResetCause();
SysCtl_clearResetCause(SYSCTL_CAUSE_POR | SYSCTL_CAUSE_XRS);
resetSource = SysCtl_getResetCause();

Regards,

Mehran

TMS320F28388D: How to properly secure RAM/Flash

jimj2713 — Wed, 03 Jun 2026 18:00:20 GMT

Part Number: TMS320F28388D

Running the dcsm_ex1_secure_memory_partition demo. I uncommented out the memory sections in the dcsm_ex1_f2838x_dcsm_z1otp.asm file, and I have set all of the GRABSECT and GRABRAM sections to 01 (all bytes 0x5), which allocates all of the Flash/RAM to zone 1.

In the dcsm_ex1_secure_memory_partition.c example file, the debugger shows all of the error-status variables are 0, which indicates LS2 and LS4 are part of zone 1, and that zone 1 is secure, yet the example code can still write to the Zone1_Locked_Array which resides in LS2.

I have verified the OTP memory areas are programmed as the asm file describes. With Zone1 confirmed as secure, and GRABRAM showing all fields as 01 (allocate CPU1 RAM to Zone1), is there something else I should look at to figure out why LS2 is still writable?

Thanks,

Jim

F29P329SM-Q1: f29 MCAN MCAL bus off recovery method

Shuqing Zhou — Wed, 03 Jun 2026 14:41:05 GMT

Part Number: F29P329SM-Q1

Hi team,

I ask this for my customer.

My customer is developing the f29 based on mcal(F29H85xMCAL-01.04.01.02

Now customer is debugging recovery process when the CAN in BusOff stage. They find if device enter the BusOff stage, even the hardware clear the Tx pending stage, the software isn’t clear the txPendingStatus because it isn’t generate the TCF ISR.

So they want to check if we can set the MCAN_TXBCIE to enable the TCF interrupt, then they can clear the txPendingStatus in the ISR.

Could you help to check if it can enable the MCAN_TXBCIE? If can’t, do we have the recommended operation to recovery from the BusOff stage?

BRs

Shuqing

TMS320F280039: How to define the struct variable is aligned by 4 bytes?

Shuqing Zhou — Wed, 03 Jun 2026 14:38:05 GMT

Part Number: TMS320F280039

Hi team,

I ask this for my customer.

Because of RAM space is not enough, so they're optimize the memory allocation.

Orignally, they define a CAN related struct variable in GSRAM, and want to move it to LSRAM.

but after the modification, the CAN communication isn't work and code will run away(CAN related function isn't use DMA or CLA, so in my understanding, this struct variable can be placed in GSRAM and LSRAM)

So i assume may be struct variable is not aligned by 4 bytes. I ask them do below modification:

in cmd, define align(4)
#pragma DATA_ALIGN(canMsgTabPublic,4) to define the canMsgTabPublic

Is above modification is correct?

After did above modification, the cpu can enter ISR periodly, but CAN communication still bad

Do you have any comments for this?

BRs

Shuqing

F29P329SM-Q1: Why the Config Variant in CDD_PWM can't be change?

Shuqing Zhou — Wed, 03 Jun 2026 14:30:54 GMT

Part Number: F29P329SM-Q1

Hi team,

I ask this for my customer.

In Wdg MCAL, Config Variant can be change

but in CDD_PWM MCAL, it can't be change, just one choice

customer have different hardware version, so they want to use the postbuild, why our MCAL don't suppot this? I check the latest MCAL(F29H85xMCAL-26.00.00.06

How to meet customer's requirement?

BRs

Shuqing

CODECOMPOSER: Change terminal font in CCS Theia

Gabor Szabo — Wed, 03 Jun 2026 12:27:53 GMT

Part Number: CODECOMPOSER

Hallo,

is it possible to change only Terminal font in Code Composer Studio Theia (my exact version is 20.4.1.4)? There is an option for it terminal.integrated.fontFamily:

Terminal › Integrated: Font FamilyModified in: Workspace
Controls the font family of the terminal. Defaults to Editor: Font Family's value.

It says that it just defaults to editor font, but I can set anything, the font in terminal is always the same as the one set for Editor (even size cannot be changed separately). So this function seems not working.

Any idea? Thank you.

TMS320F28P550SJ: How to know if the device has been reset by the external nXRS?

Wayne Huang — Wed, 03 Jun 2026 11:43:07 GMT

Part Number: TMS320F28P550SJ

Hi champs,

I am asking this for our customer.

The user uses CCS 20.5.1. Run-> Reset -> Sysem Reset to emulate reset and see RESET.XRSn is set initially.

Then, change script to boot to flash and set a breakpoint at 0x80000.

When it stops at 0x80000, the user sees RESET.XRSn is cleared.

It seems RESET.XRSn is cleared by TI boot ROM?!

Questions

Does TI boot ROM clear RESC.XRSn?
How to know if the device has been reset by the external nXRS?
Can the user just see if register RESC.XRSn is set at the beginning of main()? From CCS emulation above, it seems this fails....