https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/<p style="display:none;">blank</p>en-USTelligent Community 13https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1676170/tms320f28388d-tms320f28388d-spll_3ph_srf-loop-coefficients-calculations-and-filter-limiter/6463737Wed, 26 Aug 2026 16:51:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:34607d87-36e3-4db4-8465-324bebbe323cVenkata Praneeth SominaApologies for the delay and thanks for understanding.https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1676467/am2631-q1-qspi-flash-uart-sbl/6463717Wed, 26 Aug 2026 16:40:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:cc9d36ca-b372-4064-afa1-b28cd591a098Roi GerstelHi Lakshya, At the first stage the write happens in the app, so this is the one I was talking about - after this succeeds the next write should happen from the SBL (not tested yet since the firat stage failed). I will look at the sample and let you know if something is different on our end. Just to clarify - when you say the &quot;QSPI config&quot;, do you mean syscfg, config from code afterwards, or something else physical on the launchpad? Thanks for the quick reply! Roihttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1676909/tms320f2800156-q1-after-a-dint-eint-operation-adc-s-first-soc-s-result-doesn-t-updateWed, 26 Aug 2026 16:15:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:cdf43cc2-e44d-4c0b-94fd-055d8a5b14fcA.WPart Number: TMS320F2800156-Q1 Hi I&#39;m using F2800156 for motor control. In our program, we have a DINT&amp;EINT operation, when motor stops, and write DTC to external EEPPROM. DINT &amp;EINT is used when we put data to fifo of SPI. But this situation will sometimes cause the first ADC result doesn&#39;t update, and motor can&#39;t run again. However the other ADC sampling result is OK. Does DINT &amp; EINT opeartion have something related to the ADCA sampling? It is not easy to repeat this issue. We clear the overflow flag at the end of ADC ISR. PWM frequency is 20KHz, and the ADC ISR execution time is about 30us. The DINT &amp;EINT operation is about 7us. Pls check if there is any suggestion. Regards ArrowTMS320F2800156-Q1https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1676543/c2000ware-sdk-json-missing/6463613Wed, 26 Aug 2026 15:37:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a048f8b8-7f08-4d9f-956e-2dd0b527ee82Gary ReichlingerYes, V26.1 is installed on the local disk. The example was loaded into CCS from the driverlib in that installation. The only subfolder in .metadata (under the C2000 folder) is tirex.https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1676874/tms320f28386d-driverlib_cm-ethernet-c-compiler-warning-on-newpktptr-in-ethernet_retrieverxpacketWed, 26 Aug 2026 15:27:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5a3de5bc-3da7-451f-a27f-b4152bb097daErnst van der PolsPart Number: TMS320F28386D Other Parts Discussed in Thread: C2000WARE Dear support team, In an attempt to make my build free of compiler warnings, I have one warning left in the driverlib_cm, regarding variable &#39;newPktPtr&#39; being set but not referenced. Environment CCS 21.0.0.14__1.12.0 C2000Ware 26.01.00.00 Compiler ti-cgt-arm_20.2.7.LTS Device F2838x Issue File : driverlib/f2838x/driverlib_cm/ethernet.c line 2813 Warning : #552-D: variable &quot;newPktPtr&quot; was set but never used Function : Ethernet_retrieveRxPacket(..,..) Analysis Under certain conditions the Rx packet that is returned by the function is first handed to the application via a callback function. The &quot;newPktPtr&quot; is the returned result of that callback function, but after the assignment without further use. The Ethernet_retrieveRxPacket function always returns the &quot;pktPtr&quot; with the packet popped from the queue. Depending on the intention / requirements of this API, either: the &quot;newPktPtr&quot; should be returned (then this issue is a bug); or the returned &quot;newPktPtr&quot; is indeed of no use (and the warning can be suppressed by replacing &quot;newPktPtr&quot; with a cast to void or similar). Since I am not familiar with the details of this API, I leave further analysis to you. Obviously, there is no rush on my side regarding this issue. Regards, ErnstIndustrial AutomationC2000WareTMS320F28386Dhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1675818/f29p329sm-q1-f29-power-consumption-calculator/6463531Wed, 26 Aug 2026 14:32:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2c99a7bd-38a6-4db6-bec1-bf2762c5af54Aishwarya RajeshShuqing, We do not have such a calculator, but the numbers in the datasheet provide all the context needed for the users to measure their power consumption against the datasheet. In addition, modifying the frequency of a peripheral will not have a marginal difference in its current consumption. The reason for this is this value is primarily dependent on the input clock to the peripheral (ie. SYSCLK). The different power values for the different frequencies across the device series is already provided in the datasheet. Best Regards, Aishwaryahttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1674572/tms320f2800157-sending-multiple-24bits-frame-through-spi-consecutively-with-ncs-pulled-high-in-between/6463523Wed, 26 Aug 2026 14:27:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:113896d9-b16c-409e-9df0-bb1b1fe31307Aishwarya RajeshMahmoud, No, that is not present. Best Regards, Aishwaryahttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1676590/tmdscncd28379d-tmdscncd28379d-porting-universal-motor-control-lab-f28002x-sensorless-foc-to-f28379d-on-custom-wolfspeed-sic-power-stage/6463473Wed, 26 Aug 2026 13:54:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:db3fef94-6646-41e4-a38d-a9963bdd6bb1Masoud FarhadiThe expert is out of office. please expect the response on Friday for this thread. Best Regards, Masoudhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1676754/f29h850tu-flash-bank-mode-presents-as-bm0-in-hs-kp/6463460Wed, 26 Aug 2026 13:48:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:0056165a-8b9d-4f40-a054-914798866cdbArpit VarahmihirHi Beat, Let me look into the issue and get back to you. Regards Arpit Varahmihirhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1676706/launchxl-f28p65x-query-on-routing-clb-output-to-epwm-trip-input/6463441Wed, 26 Aug 2026 13:34:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:116b2116-1427-4520-8f53-f81add42cea7Venkata Praneeth SominaHi Sayali, Thanks for detailed explanation. Can you share your complete CLB configuration? Regards, Praneethhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1676194/tms320f28p650dh-loading-hex-with-ccs-is-very-slow/6463413Wed, 26 Aug 2026 13:11:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d25310b4-0dec-4c15-8979-6cd729671576Arpit VarahmihirHi Hang, This is expected behavior tied to how the ASCII hex format gets loaded, not a defect specific to F28P650DH. Root cause: When CCS loads a .out file, the debugger reads the COFF/ELF section table directly and writes each section to flash as a small number of large, contiguous blocks over JTAG. A .hex/TI-TXT file is plain ASCII text. CCS has to parse it line by line and convert each record back to binary, and each record only carries a small number of bytes (commonly 16–32) tagged with its own address. If those records aren’t perfectly contiguous, the flash plugin ends up doing thousands of small, separate writes (and associated overhead) instead of a handful of large ones, which is why the slowdown is observed while loading it. We’ve seen a similar pattern on a UniFlash case: the hex file was writing only 0x20 bytes at a time across widely spaced address ranges, and because there were so many discontinuous data segments, the total load time was far higher than a .out load of similar size. e. [Intel Hex image files - generating with CCSv6 and flashing using UniFlash — https://e2e.ti.com/support/tools/code-composer-studio-group/ccs/f/code-composer-studio-forum/461531/intel-hex-image-files —generating-with-ccsv6-and-flashing-using-uniflash] It’s also worth noting that Hex Utility settings aren’t inherited automatically the way compiler/linker options are — a default Hex2000 configuration can end up less efficient (and in some cases produce not-quite-correct output) than a manually tuned one. [TMS320F28377S: Flash read in jtag is not the same as generated intel hex file — https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/784177/tms320f28377s-flash-read-in-jtag-is-not-the-same-as-generated-intel-hex-file ] Recommendation: For everyday CCS debug loads we would recommend using .out directly rather than enabling Hex2000. The Hex/TI-TXT format is intended for external programming paths (UniFlash, third-party programmers, SCI/I2C/CAN serial bootloading) per the Hex Utility documentation in the compiler manual and the serial boot app note, not for CCS’s own debug-time flash loader. [Getting Started with Bootloading on C2000 ™ Microcontrollers (User’s Guide, SPRUJH3) -&gt; https://www.ti.com/lit/ug/sprujh3/sprujh3.pdf — covers hex2000/C2000 Hex Utility configuration and post-build step setup for on-chip flash bootloaders.] [Serial Flash Programming of C2000 Microcontrollers (SPRABV4, Rev. F) -&gt; https://www.ti.com/lit/an/sprabv4f/sprabv4f.pdf — describes generating boot-format hex/TXT files via hex2000 for SCI/I2C/CAN/SPI serial boot flows, not CCS debug loads.] You can also check out similar e2es on similar issues: TMS570LS0914: Hex File Takes Excessive Time to Flash on Microcontroller — https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1453268/tms570ls0914-hex-file-takes-excessive-time-to-flash-on-microcontroller TMS320F28P650DH: The generated .hex and .bin files are different after being loaded to FLASH — https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1434496/tms320f28p650dh-the-generated-hex-and-bin-files-are-different-after-being-loaded-to-flash Regards, Arpit Varahmihirhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1676807/tms320f28p550sj-f28p55_generic_timeseries_anomalydetectionWed, 26 Aug 2026 13:02:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:aee2e654-1af1-42ac-bdfc-872ce832f3a7Jozef SedivyPart Number: TMS320F28P550SJ Other Parts Discussed in Thread: C2000WARE I&#39;m working through example project F28p55_generic_timeseries_anomalydetection and have run into two separate issues. Any confirmation/guidance on either would be appreciated. 1) Inference appears to be running on CPU, not NPU My application does not call `TI_NPU_init()` before `tvmgen_default_run()`. I measured the duration of the `tvmgen_default_run()` call itself using a cycle counter around the call: it takes approximately 5,000,000 system cycles. At 150 MHz that&#39;s ~33.3 ms. For a small autoencoder (100-sample input), this seems far too slow for genuine NPU-accelerated execution, and I suspect the model is actually executing as generated CPU C-code rather than being offloaded to the NPU peripheral. Could someone confirm: - Is `TI_NPU_init()` required for the generated model to actually dispatch to the NPU, or does `tvmgen_default_run()` handle NPU dispatch internally regardless? - Is ~33 ms consistent with a CPU-only fallback for a model of this size, versus expected NPU execution time? - How can I verify from the generated codegen output or build log whether the model was actually compiled/targeted for NPU vs CPU in C2000Ware 26.01.00.00? 2) Reconstruction error never drops below threshold Setup: signal generated by an external AW Generator, sampled via ADC on a 100 Hz timer-triggered ISR, 100 samples per inference window, normalized to p.u. before feeding the model. I first tried a 1 Hz input signal (100 samples = 1 full period), per my understanding of the example&#39;s documented assumption. Reconstruction error stayed above threshold. I verified my sampling ISR timing directly: 1,500,000 cycles between ISR entries at 150 MHz = exactly 10 ms = 100 Hz, so the sampling rate itself is correct. I then compared my captured 100-sample ADC window against the project&#39;s own shipped golden test vector (`raw_input_test[100]` from the example&#39;s C test data). Zero-crossing and autocorrelation analysis of that golden vector shows a dominant period of ~10 samples, i.e. approximately 10 full cycles across the 100-sample window - not 1 cycle as I expected for a 1 Hz signal at 100 Hz sampling. This suggests the model was actually trained assuming a ~10 Hz input signal (10 samples/cycle, 10 cycles/window) rather than 1 Hz. When I fed a 1 Hz signal, reconstruction error got worse; a signal closer to 10 Hz produced a closer (but still above-threshold) match to the golden vector shape. Could TI confirm: - What is the actual intended/trained input signal frequency for this example (1 Hz or 10 Hz at 100 Hz sampling)? - Is there a documentation mismatch between the stated &quot;1 Hz signal sampled at 100 Hz&quot; assumption and the actual golden test vectors shipped with the example? Used documentation: ( https://github.com/TexasInstruments/tinyml-tensorlab/tree/main/tinyml-modelzoo/examples/generic_timeseries_anomalydetection) Thanks in advance. JozefTMS320F28P550SJC2000Warehttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1675656/f29h850tu-core-3-stuck-in-nmi-after-power-cycle/6463385Wed, 26 Aug 2026 12:53:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:88bc1810-a913-4c92-b3fb-ff1c8817f1adMahmoud MegawerHi, I&#39;ve tried two different scenarios: 1. power cycle the board with an ePDU script, and this is the result: a lot of error and the board disconnected 2. power cycle the board manually (power on/off the board physically). the board was working properly and shows free running on CCS.https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1676467/am2631-q1-qspi-flash-uart-sbl/6463377Wed, 26 Aug 2026 12:44:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:e667aaac-62bc-4a42-ad03-b2f658950512Lakshya VermaHI Roi, This Flash_ write ( ) API call which you are mentioning i s this being used in the application or sbl ? There is example regarding how to do flash write in below example &quot;mcu_plus_sdk_am263x_26_00_00_06\examples\drivers\qspi\qspi_flash_transfer&quot; The configuration of QSPI should be like in this example at the moment when you are trying to perform Flash write.https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1676592/launchxl-f28p65x-single-block-hex-file-creation-in-post-build-steps/6463343Wed, 26 Aug 2026 12:05:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ac297abd-724c-4ab5-b859-0d0d3bc93ee8Shaunak DeshpandeHi Subhash, I have assigned the query to the expert, they are OOO due to festivals, please expect a slight delay in response Regards, Shaunakhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1669826/tms320f28p650dk-f28p65x-with-single-port-ethercat-design/6463341Wed, 26 Aug 2026 12:04:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5bc97a7c-5095-4e9c-8866-980fd27b3a86AndreTsengBased on test result today, PHY reverse loopback test passed. The issue is isolated to MII interface in between DP83826E and ESC. rxFrameError of ESC register will be increased when EtherCAT master perform device scan. Need PHY team to help review layout design. Regards Andrehttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1676771/tms320f28379s-ram-retention-after-warm-resetWed, 26 Aug 2026 11:57:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:6f2d80d4-1690-485a-ab34-f2d5e5e65bedWayne HuangPart Number: TMS320F28379S Hi Champs, The user needs to have RAM retention function after warm reset including watchdog reset and external nXRS pull low. We are aware of this RAM initialization on boot-ROM. Is there any workaround to have RAM retention after warm reset including watchdog reset and external NRST pulled low? We are thinking of jumping to flash entry on an watchdog ISR to bypass boot-ROM, but it seems it still cannot solve software hang by watchdog reset or external NRST pulled low. Do you have any suggestion?TMS320F28379Shttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1676754/f29h850tu-flash-bank-mode-presents-as-bm0-in-hs-kpWed, 26 Aug 2026 11:19:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b747994a-fb75-411e-b632-8e6d5aac5419CodeSkinPart Number: F29H850TU Hello TI experts, On a TMS320F29H850TU9 ( REVID at 0x30180028 = 0x1 , silicon revision A) that was configured for flash bank mode 2 in HS-FS, the bank mode presents as mode 0 throughout the HS-KP state. BANKMODE at 0x3008005C reads 0x00000009 (BM2) in HS-FS but 0x00000003 (BM0) once the part is in HS-KP, and the BANKMGMT records at 0x10D80000 / 0x10D84000 read back 0x00000000 (access denied) in HS-KP. Our objective is to provision from HS-KP to HS-SE in a single session, programming the security configuration and the application (including CPU3 / FLC2) without an intermediate reset. Can you confirm the bank-mode behavior above, and advise how to have bank mode 2 available in KP so that a security configuration, CPU1 and CPU3 content can be programmed in that single session? Also, while in HS-KP, is it possible to determine the bank mode the device was in before it transitioned into HS-KP, and thus the mode it will be in once it transitions out? Thank you, BeatF29H850TUIndustrial Automationhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1676706/launchxl-f28p65x-query-on-routing-clb-output-to-epwm-trip-input/6463267Wed, 26 Aug 2026 10:40:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:173cbd6d-3551-4b25-ac69-d9eb37808ae6Sayali DeshmaneHello Praneeth, My requirement is that the ePWM output should operate normally when the CLB Tile logic output is LOW . Whenever the CLB Tile logic output becomes HIGH , it should be treated as a fault condition and immediately trip the ePWM output , forcing the PWM to the configured safe state. In summary, the expected behavior is: CLB Tile logic output = LOW → ePWM operates normally. CLB Tile logic output = HIGH → ePWM is tripped and PWM outputs are disabled/forced to the configured state. I am looking for the recommended method to achieve this functionality using the CLB output on device. Thanks!!https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1676706/launchxl-f28p65x-query-on-routing-clb-output-to-epwm-trip-input/6463240Wed, 26 Aug 2026 10:10:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:590532e3-7ed3-45ba-8291-5f611d0486d1Sayali DeshmaneHello Praneeth, Thanks for the quick response. I also tried configuring the Overriding Outputs option in the CLB by selecting Output 1 , with the expectation that the ePWM output would be overridden whenever the logic implemented in the CLB Tile Lookup Table goes high. However, after enabling the override, I am unable to observe the expected ePWM waveform even under normal operating conditions (when no fault is present). The PWM output is not behaving as expected, making it difficult to verify the trip functionality. Could you please advise if there are any additional configurations required when using CLB Overriding Outputs with ePWM. or if there is a recommended approach to use the CLB output as a trip source for ePWM. Thanks!!