https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/<p style="display:none;">blank</p>en-USTelligent Community 13https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1661798/tms320f2800154-q1-safety-mechanismn-to-detect-transient-faults-for-cpu1mem_lsx/6412422Fri, 10 Jul 2026 14:03:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:db710b5c-c01e-445e-9f2a-b5bd7f918514Gus MartinezHi Filip, Please ensure SRAM2 (SRAM parity) and SRAM16 (information redundancy techniques) are enabled as safety mechanisms. Both can detect transient faults.https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1659309/tms320f280039c-new-project-compiler-error-for-lfu-application-10099_d/6412349Fri, 10 Jul 2026 12:58:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8165a6fb-7313-4870-b984-b8389a446ec0Ira TheteHi Yuan, Can you try the following 1. If you remove the path to the old project&#39;s .out file from -lfu_refrence_elf field, are you able to build the new project? 2. If you remove all LFU related flags (so --lfu, --lfu_refrence_elf, --lfu_default etc) from CCS Project Properties -&gt; C2000 Compiler does the new project build? This will help us identify if the issue is with LFU mechanism or the new project itself. If new project builds successfully on its own (without LFU) and the issue only started happening after we referenced the old project for LFU, then can you please build the new project normally on its own (without referencing the old project&#39;s .out file) and check the generated .map file Can you please share that? Or specifically check the size of TI.ramfunc. Compare this with the old project&#39;s .map file. Also check what is inside TI.ramfunc in the .map, make sure it is not bloated up/ unexpected components have not appeared there If possible, share the old and new project&#39;s .map file with us (if new project builds without LFU and can produce a .map file) NOTE - Please make sure that only one linker cmd file is included in the build when you are building the new project. Thanks, Irahttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1663209/f29h850tu-epwm-trigger-mixed-eventsFri, 10 Jul 2026 11:57:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:b4794b99-220e-4111-9c11-675c604d3886Marco SchmidPart Number: F29H850TU Other Parts Discussed in Thread: SYSCONFIG I am using SysConfig V1.27.1 with SDK V26.0.0 to set up an ePWM triggered Interrupt. I wanted to use the Mixed Event Signal to use 2 different Events to trigger an Interrupt. As &quot;Mixed Interrupt Event Sources&quot; I set &quot;Time-base counter equal to CMPA when the timer is incrementing&quot; and &quot;Time-base counter equal to zero&quot;. While doing this, I noticed, that the ENTMIXEN register already sets the bits for PRD (Time-base counter equal to Period) and ZRO (Time-base counter equal to zero) set to 1 by default after a reset. See also the TRM: The settings in SysConfig then only add more Event sources to the Mixed Event. That means, that even if I would set no &quot;Mixed Interrupt Event Sources&quot; in SysConfig, I would still trigger Interrupts if the Time-base counter reaches zero or period. This seems counterintuitive to me.F29H850TUSYSCONFIGhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1661675/tms320f280037c-lin-sci-mode-baud-rate-divisor-example-is-confusing/6412279Fri, 10 Jul 2026 11:46:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:cd1daa8e-3350-4e29-b38f-b9fa02bfbdcaGenatcoHi Delaney, There is a discrepancy in the web online LIN text states the LENGTH register is LIN mode only but as you can see in the above post register [18:16] states SCI mode too. Some people actually read the TRM text ;-). So, LIN is currently in 10-bit simple mode, disabled parity, one stop, 9600 BPS. LIN_setBaudRatePrescaler(LINA_BASE, 782U, 10U). Getting random framing FE on OE errors. P=SYSCLK/16 or 7.5mHz peripheral clock speed and fine tune via M but the U register never gets set, only M &amp; P are being configured in this case NORMAL configuration mode. The wording below states there is internal VCLK but it is only a clock source (divider) not a clock! Anyhow, LIN is receiving ASCII characters 9600 BPS in RX/EMU registers only. CCS debug mode emulation false or true does not matter. The function below does not read any buffered CHAR when RX register is polled. The RX register data we see in debug is not ever retrieved by the command LIN_readSCICharNonBlocking(LINA_BASE, 0) in multi-buffer or disabled mult-ibuffer mode. This LIN SCI mode is not a true SCI module as it expects a specific data format in idle mode which seems to be SIMPLE data frame mode expects certain bit spacing? The remote sender does have delay time after each word is transmitted but 10 bits is anyone guess. The LINSCI is not in address mode does RX still require 10-bit time spacing in SCI Idle time mode? Can you verify why that occurs on a x39c launch pad? It seems LIN SCI mode is invasive with CPU clock cycles when polled via CPU timer 250ms, 500ms. LIN demands 5ms or less time slot or the FE, OE flags start to toggle after R/WIC clearing. Still no data is being read from the RX register as SCIB FIFO mode did very easily this same task. Perhaps LIN is ghosting the RX/EMU registers in debug after asserting preformLINreset() when FE or OE flags set? If the emulation error flags are late, does the RX data registers get zeroed? The TRM does not say anything relative about the error flag emulation mode! The RXRDY flag is not being cleared polling the multibuffer mode in either debug emulation mode of XDS110 probe. It also locks up when the MCU clock source is stopped X1 input from another MCU. We have to exit CCS debug each time that occurs or XDS110 cJTAG mode probe Launch-39c will lock up CCS v12.8.1. The RX non-blocking debug (emulation) text is vague in the clarification what it actually does as the receive register shows characters, set true or false. It would seem LIN cannot be debugged by that text wording when set false it should stop after the last buffered character, but it doesn&#39;t in either, mode. Obviously, the TRM text does not match the XDS110 emulator behavior. That is a real head scratcher!https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1663055/tms320f28p650dk-clb-synchronization-requirement/6412264Fri, 10 Jul 2026 11:30:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:de3375bf-ab2d-4f0e-8284-a9d5d01cec45Venkata Praneeth SominaHi Liu Thanks for reaching out. I will get back to you in a day or two.https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1663200/launchxl-f28379d-epwm1b-high-output-in-idle-stateFri, 10 Jul 2026 11:21:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:8df344f2-56c9-43d4-af1d-2558804944aaKayala Naga Venkata SandeepPart Number: LAUNCHXL-F28379D Other Parts Discussed in Thread: SYSCONFIG I AM USING LAUNCHXL-F2837D launchpad in this i want to create a complementary pwm ouput when in the IDLE state EPWM1A output is low and EPWM1B is high i want to both should low in the idle mean when PWM is off how can achive without the trip zone approch. is there any setting in the SYSCONFIG tool please helpLAUNCHXL-F28379DSYSCONFIGhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1662442/tms320f28p650dh-fir-filter-design-tool/6412250Fri, 10 Jul 2026 11:20:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:413987d9-3300-465e-be11-d9b8db8d3096HS FAE GermanyHi Ira, I found the the pyfda tool and will play with it to get the coefficiences. github.com/.../releases Regards, Holgerhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1663198/tms320f28386d-mdio-clock-csr-clock-sourceFri, 10 Jul 2026 11:19:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c778fb56-00b0-4063-8c7b-76b19becab19Ernst van der PolsPart Number: TMS320F28386D I have exactly the same question as Markus A : TMS320F28388D: MDIO clock: CSR clock source? , although I am using the F28386. The &quot;CSR clock&quot; mentioned in www.ti.com/.../spruii0f.pdf is not defined in that TRM. Unfortunately, that question has not been answered. Strangely enough MS CoPilot suggests that the CM clock is the source of the CSR clock, referring to the question of Markus A. I did some measurements to verify this suggestion, selecting different settings for the CR field in the MAC_MDIO_Address Register, with the same clock configuration as Markus: CPU 1 clock = 200 MHz AUX clock = 125 MHz CM uses AUX clock Ethernet clock = System clock with divider 2 = 100 MHz MDIO Clock Measurements CR divider MDIO clock frequency 0001 62 2.0 MHz 0011 26 4.8 MHz 1000 4 31.25 MHz As you can see, a value of 125 MHz for the CSR clock fits the measured MDIO clock values best. So, until TI declares otherwise, I assume CoPilot&#39;s suggestion is correct and the &quot;CSR clock&quot; is equal to the CMCLK, or to be more precise the CM.PERx.SYSCLK for the Ethernet peripheral.TMS320F28388DTMS320F28386DEMAChttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1663184/tms320f28p559sj-q1-why-the-xint-interrupt-isn-t-triggerFri, 10 Jul 2026 10:41:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9915a057-257b-49a7-9af5-621d0daceb5bShuqing ZhouPart Number: TMS320F28P559SJ-Q1 Hi team, I ask this for my customer. My customer want to use XINT to record the external input signal edge number. We refer to the demo in C:\ti\f29h85x-sdk_26_00_00\examples\driverlib\single_core\gpio\gpio_ex3_interrupt. we change the interrupt io is gpio29, interrupt type is both edge. But after we input the pluse signal in the gpio29, the interrupt isn&#39;t generate We check the XintRegs.XINT1CTR, it count continuous, the PIEIER1.4 is 1 that means XINT1 is enabled, INTM is 0 means global interrupt is enabled, XINT1CR is 0xD Could you help to check this and provide a demo that CPU will enter the interrupt when it detect the edge change? BRs ShuqingTMS320F28P559SJ-Q1https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1662283/tms320f28375d-xds110-fails-to-drive-trst-high-with-2-2k-pull-down---any-fix-without-hardware-changes/6412108Fri, 10 Jul 2026 08:19:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:02750d74-a294-40bd-8982-9d35aaec9241Michael VHi Matthew, Thank you for your response. As expected, option #1 (adding a buffer) would have been the preferred solution. However, after further review, the customer confirmed that they are unable to implement this due to very tight space constraints on their adapter board. As an alternative, they proceeded with option #2 by adding a 6.8 kΩ pull-up resistor. Unfortunately, this did not resolve the issue, and they encountered the same programming error as previously reported. Questions: Does this signal that the drive strength is still insufficient, or are we possibly running into the VIH threshold issue? Could you please advise if there are any additional recommendations or alternative approaches we could consider? Thank you for your support, and I look forward to your response. Best regards, Michaelhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1663113/tida-010957-request-for-example-code-for-tida-010957-2Fri, 10 Jul 2026 07:51:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:6c61a322-fdd2-4008-ab75-51da80dac438Jiheon HongPart Number: TIDA-010957 Hi, I am currently studying the TIDA-010957 reference design (15kW Bidirectional Three-Phase plus Neutral Flying Capacitor based on GaN) I have gone through the design guide and the application note (SDAA195) in detail, and I would like to proceed with firmware implementation on a C2000 MCU. Could you let me know whether TI provides any example code or firmware project for the TIDA-010957 Thank you.TIDA-010957https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1662781/am2611-q1-why-the-reference-design-don-t-follow-the-hardware-desgin-user-guide/6412024Fri, 10 Jul 2026 06:54:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:3db29feb-20e8-455b-9212-89131d480e27Tejas KulakarniHi Shuqing, As per the same hardware design guideline, the capacitor numbers mentioned &quot;are reasonable starting points for any AM263x, AM263Px, or AM261x PCB design. However, due to specific PCB routing differences and the resulting plane capacitance and decoupling mounting inductances and other parasitics, TI highly recommends that designers simulate and measure the specific power distribution network performance&quot;. So based on these PDN simulations(also covered in the same document), we have different numbers in our EVMs Hope this makes it clear. Thanks, Tejas Kulakarnihttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1663055/tms320f28p650dk-clb-synchronization-requirementFri, 10 Jul 2026 06:12:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:58008292-8dd1-4aac-b4d7-2a126545204cLIU LIUPart Number: TMS320F28P650DK Hi TI support team, Based on Figure 12-3 in TMS320F28P65x TRM, CLB Clock can be configured to SYNMODE or ASYNMODE with the SYSCLK. When I configure CLB to ASYNCMODE: Is Column Synchronization Requirement of Table 12-2. Global Signals and Mux Selection still valid? IF the input signal comes from other modules, I need configure CLB_INPUT_FILTER.SYNC =1 , instead of referring to the Table 12-2? If I misunderstand, please explain why comlumn Synchronization Requirement of Table 12-2 is still valid in ASYNCMODETMS320F28P650DKhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1658365/tms320f28388d-issue-with-can-example-code-on-f28388d-can-communication-not-working/6411907Fri, 10 Jul 2026 05:06:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:edc4a9a3-3ac6-4a19-9493-1a4c1ba70786Phani ChaluvadiHi Joseph, I checked the register values on Node 1. MCANSS_STAT.ENABLE_FDOE = 0 MCAN_PSR = 0x00000748 DLC = 4 Payload size = 4 bytes Please let me know if you need any additional register values or further details.https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1660342/f29h859tu-q1-unexpected-behavior-of-pipe-overflow_flag-with-cputimer/6411839Fri, 10 Jul 2026 03:40:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:16a582ed-8028-43f8-8696-1f3444da3904Aishwarya RajeshFrancois, Thanks for the information. I used one of the existing timer examples and see the PIPE OVERFLOW and CPUTIMER TIF flags being set. TLDR: I need to consult with a colleague on one more thing on why exactly the OVERFLOW is always being set, sorry for the delay. In regard to the TCR.TIF flag, the screenshot from the TRM shared in my earlier comment confirms this flag gets set when the CPU-timer decrements to zero. TIF is not cleared automatically and does not need to be cleared to enable the next timer interrupt. In other words, this is the intended behavior. You could optionally use CPUTimer_clearOverflowFlag() to clear this flag. In regard to the INT_CTL_L[8].OVERFLOW_FLAG, it is a similar idea. I&#39;ve attached my example I&#39;m using to test based on the configurations you provided. e2e.ti.com/.../8103.timer_5F00_ex1_5F00_cputimers.zip Best Regards, Aishwaryahttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1659309/tms320f280039c-new-project-compiler-error-for-lfu-application-10099_d/6411819Fri, 10 Jul 2026 03:07:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:180f5ecc-a683-49c0-9fee-b302c529a0dcYuan WangHi Ira 1. The CMD files has been forwarded to you via our FAE. 2.both the projects use the same - optimization level(2), linker options/flags and compiler version(ti-cgt-c2000_25.12.0A26176)https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1659470/f29h85x-sdk-f29h85x-dcl-documentation/6411765Fri, 10 Jul 2026 01:21:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:1c480ba1-ebb9-46ea-8a34-7df01a323e7bSira Rao80I apologize for the delay in responding. I am looking into this and will reply before the weekend.https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1662981/tms320f28377d-ep-epwmclkdiv-warningFri, 10 Jul 2026 01:05:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:fc979afe-c406-4c8b-8f8c-606f087e5938Kasai ShigeoPart Number: TMS320F28377D-EP Hi When EPWMCLKDIV is set to/2, the following warning appears: I checked the errata, but could not find relevant information. Please answer the following. 1) Please provide me with a document that provides detailed information. 2) Is this warning limited to a silicon version? 3) Is there a silicon version planned to fix this warning? (Warning Infomation) CPU1:EPWMCLKDIV ePWM TZFRC and TZCLR events will sometimes be missed when EPWMCLKDIV is devide by2. Always program EPWMCLKDIV to devide by 1 if using TZFRC or TZCLR register. Please refer to the F2837xD Sikicon Errata more Details. Thank you and best regards, S.KasaiTMS320F28377D-EPAerospace &amp; Defensehttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1662974/tms320f28377d-sci-bootloader-half-duplex-supportThu, 09 Jul 2026 23:59:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:64c19727-e516-4a41-878f-6e2404bb2035Greg BaghdikianPart Number: TMS320F28377D Hi, I&#39;m looking into using the SCI bootloader to perform OTA updates over a RS-422 or RS-485 link. If I use RS-485, the SCI bootloader needs to implement a &quot;direction control&quot; GPIO output to control the RS-485 transceiver; to switch between sending and receiving mode. Does the SCI bootloader support this? If not, is there any practical way to use the SCI bootloader over RS-485? I&#39;ve seen posts like this: https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/491666/c200-sci-bootloader---over-rs485 but they don&#39;t clearly state if the SCI bootloader has a direction control output. Thanks, -GregTMS320F28377DAerospace &amp; Defensehttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1649838/tms320f280039c-continuous-nmi-reset-loop-caused-by-memcpy-reading-corrupted-flash-sector-on-every-boot/6411631Thu, 09 Jul 2026 22:15:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:7c463f11-46f5-43f0-a7d8-9100b2938b44Alex WasingerTanmay, Please find attached an example of handling a Flash ECC uncorrectable error NMI Best, Alex e2e.ti.com/.../2063.flashapi_5F00_ex1_5F00_programming.c