https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/<p style="display:none;">blank</p>en-USTelligent Community 13https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1683912/am2612-how-to-get-current-time-of-icss_timesync-in-industrial-communication-sdk/6510147Wed, 14 Oct 2026 06:58:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:05f7f668-f89b-4286-a473-829e9ae7ce3aArchit DevHi Xuebin, Thank you for the clarification and patience. SYNC0 is an Industrial Ethernet Peripheral (IEP) hardware output, not a PRU-toggled GPIO. The IEP raises SYNC0 when compare register CMP1 hits. The host sets everything up once, and PRU0 firmware then reprograms CMP1 after every hit and ends each pulse. A bit more information about the flow of TimeSync: On the first Sync from the Grand Master, &quot;TimeSync_doFirstAdjustment&quot; writes PTP time into the IEP counter. &quot;TimeSync_resetIEP&quot; then sets CMP1 to the next whole-second boundary plus 1 s of margin. The PRU firmware then adds exactly one period on every hit, so CMP1 is always a multiple of the period in PTP time. Boards locked to the same Grand Master therefore raise the rising edge on the same period boundary. Their offset is the PTP sync jitter, not a fixed fraction of the period. The rising edge comes from IEP hardware, so firmware latency does not add jitter to it. The falling edge is polled by the PRU and can vary. Coming to when the output becomes aligned: Before the first adjustment, SYNC0 runs from the free-running IEP. It is not aligned between boards. After the first adjustment, the first aligned pulse appears 1 to 2 s later. Now coming to your requirement finally - in our out-of-box example, we have configured the SYNC0 interval as 1 millisecond, so if that&#39;s your requirement - no explicit configuration is needed. Also, I&#39;ve tested it on my side and verified this. Test Topology: Rockwell PLC (PTP TimeTransmitter) Port 1 -&gt; DUT1 Port 1 (PTP TimeReceiver) DUT1 Port 2 (PTP TimeReceiver) -&gt; DUT2 Port 2 (PTP TimeReceiver) All links are connected at 100Mbps, full duplex. Result: I used an oscilloscope to tap this, and I see that in steady state sync, the difference between the rising edge of the signal is 1 millisecond, on both boards. Let me know if you have any more questions/concerns here. Regards, Archithttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1688012/tms320f28388d-tms320f28388d-can-the-non-owner-cpu-read-sdfm-data-filter-results-sddatax/6510078Wed, 14 Oct 2026 06:02:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5122de6f-d6d7-4547-a707-068b8dd06e75Iv&#225;n P&#233;rezThank you, that was very helpful! I&#39;ll try it outhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1684581/tms320f28374s-tms320f28374s-tms320f28374s-periodic-sta-stl-ram-diagnostics-cerrthres-fmeda-diagnostic-used-in-application-and-sta_march_copy-false-fail-risk/6509962Wed, 14 Oct 2026 04:06:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:64d32f8d-9dee-473d-ba45-8bca6c4dcaf6MatthewPate1. DTI and Count Window Your setup looks reasonable. A 420 ms count window (one full sector sweep) clearing CERRCNT after each pass is a sensible way to bound the accumulation interval. DTI = 20 min is the detection deadline for the Safety Logic block, and your 420 ms sweep is well inside that, so documentation-wise you are covered on the timing side. One thing worth noting in your safety case: SRAM3 (Software Test of SRAM) currently set to 0 assumes March runs at POST only. That is fine for the flag itself, but your safety case documentation should call out explicitly that POST-only execution means faults introduced after power-up are not caught by that mechanism until the next power cycle. Whether that is acceptable depends on your mission profile. 2. Environmental Error Rate and Raw Transient FIT Using Raw Transient FIT from Details-IEC61508 column P as your background-rate baseline is a reasonable starting point. A few things to be aware of before you finalize that number: The FMEDA has a flux factor input at FIT_Estimation:H9 (default = 1, calibrated to New York City sea level per JESD89A). Entering your deployment flux factor there will scale the neutron component of the transient FIT automatically, and the updated values will flow through to Details-IEC61508 column P for M0/D0/D1. You will need to derive the flux factor from JESD89A yourself based on your deployment altitude and geography; the spreadsheet does not include a lookup table. One important caveat on what the flux factor does and does not adjust: the Raw Transient FIT has two components, alpha and neutron. At sea level for M0/D0/D1, the split is roughly 60% alpha and 40% neutron. The flux factor only scales the neutron portion. The alpha component is fixed from TI process characterization data and does not vary with altitude or geography. For a sea-level or low-altitude deployment, alpha is actually the dominant contributor, and the flux factor adjustment will have limited effect on the total. So yes, your use of Raw Transient FIT as a baseline is appropriate, taking into account the above as needed. Also, you can document in your safety case that the alpha rate comes from TI process characterization data and that your environmental assumption for the neutron component is based on JESD89A at your deployment altitude. Defining that assumption is the responsibility of the system integrator per SPRUI78D 2.2.3/2.2.4. 3. N = 2 / 420 ms Window The method is sound. A windowed count with single-transient immunity is a standard approach for distinguishing transient soft errors from degrading cell behavior. On the specific value of N = 2: TI cannot validate a particular threshold as &quot;correct for SIL2,&quot; since deriving N against your PFH budget is part of your safety case, not ours. What I can say is that the approach is consistent with the intent described in TRM 3.6.6 and with general practice. To complete your own validation of N = 2, the math you would want to walk through: With your adjusted background FIT rate (post flux-factor update if applicable) and a 420 ms window, compute the expected number of correctable events per window. If that number is well below 1, then N = 2 gives you roughly (rate)^2 residual probability of a false pass per window, which for a degrading-cell scenario producing elevated but sub-2 count would be the relevant missed-detection case. Confirm that residual probability, accumulated over your DTI and mission profile, stays within your PFH allocation. If you have already done that math and it closes, N = 2 looks like a defensible choice. If you have not yet run through it explicitly, that is the step to document before finalizing. Best, Matthewhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1686796/f29h850tu-sdfm-comparator-digital-filter-configuration-problems/6509787Tue, 13 Oct 2026 22:50:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:21b43573-0619-4a9f-9d1d-4b8c7226ace7Ryan DavittHey Ondrej, Apologies for the delay. I am still working on an answer for this. I will get back to you by Thursday at the latest. Best, Ryanhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1688012/tms320f28388d-tms320f28388d-can-the-non-owner-cpu-read-sdfm-data-filter-results-sddatax/6509785Tue, 13 Oct 2026 22:49:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9fab0366-75ae-4591-962a-161057c71aadRyan DavittHello Ivan, It is my understanding that CPUSELx corresponds to the clock source, not the data path (see Section 41.3 and especially Figure 41-1). Additionally, the register description segment for CPUSEL4 (Section 3.16.9.3) directly mentions the clock path, not the data path. Therefore, if I am understanding your goal correctly here, CPUSEL4 will not have the impact you seem to be expecting. You can designate an &quot;owner CPU&quot; through the AC registers for SDFM1 and SDFM2 via value 0x3 for CPUx (owner CPU), while CPUy (non-owner) is set to 0x2 for protected read access only. Let me know if that answers your question. Best, Ryanhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1689314/tms320f28379d-unable-to-find-dcan-examples-in-c2000ware/6509757Tue, 13 Oct 2026 22:26:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:94579a27-e2e8-4346-9a73-c2d62396c8eeHAREESH JANAKIRAMANYes, that helped. Thanks Joe. you can close this.https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1689314/tms320f28379d-unable-to-find-dcan-examples-in-c2000ware/6509727Tue, 13 Oct 2026 21:53:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:a015717a-068a-4b30-9ef9-388d4aa66e9cJoe PrushingHello Haresh, great to hear from you! Can you check here and see if these are the examples for which you are looking? C:\ti\c2000\C2000Ware_ \driverlib\f2837xd\examples\cpu1\canhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1686398/tms320f28375d-tms320f28375d-dma-channel-gets-stuck-after-interrupt-driven-spi-transfers/6509706Tue, 13 Oct 2026 21:40:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d174f762-e234-446b-ada5-bdf2b42cdf80Delaney WoodwardHi Abhimanyu, Apologies for the delay, I have been out of office. Please allow me another day to get back to you with a response. Best Regards, Delaneyhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1688084/tms320f28386d-tms320f28386d-letter-of-volatility/6509705Tue, 13 Oct 2026 21:40:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9596e75c-de36-4892-9c68-632427421900Delaney WoodwardHi Riley, Apologies for the delay, I have been out of office. Please allow me another day to get back to you with a response. Best Regards, Delaneyhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1688044/tms320f28p650dk-letter-of-volatility/6509704Tue, 13 Oct 2026 21:39:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5a6dd322-203c-4cb3-8d86-56495dd64911Delaney WoodwardHi Riley, Apologies for the delay, I have been out of office. Please allow me another day to get back to you with a response. Best Regards, Delaneyhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1689314/tms320f28379d-unable-to-find-dcan-examples-in-c2000wareTue, 13 Oct 2026 21:22:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:c46fdc18-fb9c-42ff-a911-9b4de3142cb9HAREESH JANAKIRAMANPart Number: TMS320F28379D Other Parts Discussed in Thread: C2000WARE Hello TI, SPRACE5 (yes, it is an app.note I wrote) says the following: &quot;The project files and examples described in this document are available for download as part of C2000Ware&quot;. However, I am unable to find it in C2000ware. I am using C2000Ware_6_00_00_00. Can you please help? Respectfully, Hareesh Janakiraman (ex-TIer and e2e 1* guru) Embedded-Guru LLC Houston, TXC2000WareTMS320F28379DTest &amp; Measurementhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1686833/tms320f28054m-motor-vibrations/6509609Tue, 13 Oct 2026 20:02:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:11e883d5-e151-4ff9-89c6-aba7cbc1800eJiaxin TengCan you advise how did you determine the Rs value for your motor here?https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1685363/launchxl-f28e12x-c2000-motorcontrol-sdk-user_mtr1-h-parameters-setrefspeed-bypassmotorid-resetting-to-defaults-on-build-in-level-2-4/6509601Tue, 13 Oct 2026 19:50:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:91f5a024-6e9e-41d9-8949-ce10781828d1Masoud FarhadiThe real live knob is motorVars_M1.speedSet_Hz, not speedRef_Hz. speedRef_Hz is an internal working copy that is continuously re-synced from speedSet_Hz at motor1_drive.c: every ISR tick while running, then fed into TRAJ_setTargetValue (line 866) to drive the ramp generator and ultimately the open-loop output frequency. To change the output frequency live during RUN, write to motorVars_M1.speedSet_Hz instead of speedRef_Hz. Best Regards, Masoudhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1686833/tms320f28054m-motor-vibrations/6509578Tue, 13 Oct 2026 19:25:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:5ae0b8e3-c2da-402c-b8a8-6b85da0422d5Gb AdesiyunNo. I use the TMS320F28054M in a custom PCB.https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1686833/tms320f28054m-motor-vibrations/6509528Tue, 13 Oct 2026 18:41:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:f9620f0f-2728-48cd-af10-acee99a9033fJiaxin TengThanks. Do you use InstaSpin with the HV motor kit?https://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1686833/tms320f28054m-motor-vibrations/6509516Tue, 13 Oct 2026 18:36:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:d2e7d49e-790f-4b4c-b6d0-2cbd2f77dc55Gb AdesiyunHi Jiaxin, These are my motor parameters: #define USER_MOTOR_TYPE MOTOR_Type_Pm #define USER_MOTOR_NUM_POLE_PAIRS (2) #define USER_MOTOR_Rr (NULL) #define USER_MOTOR_Rs (1.892402) #define USER_MOTOR_Ls_d (0.00023) #define USER_MOTOR_Ls_q (0.00023) #define USER_MOTOR_RATED_FLUX (0.0835702) #define USER_MOTOR_MAGNETIZING_CURRENT (NULL) #define USER_MOTOR_RES_EST_CURRENT (1.5) #define USER_MOTOR_IND_EST_CURRENT (-1.5) #define USER_MOTOR_MAX_CURRENT (6.5) #define USER_MOTOR_FLUX_EST_FREQ_Hz (60.0)//100 #define USER_MOTOR_ENCODER_LINES (1024.0) #define USER_MOTOR_MAX_SPEED_KRPM (5.6) #define USER_SYSTEM_INERTIA (0.01061397791) #define USER_SYSTEM_FRICTION (0.01320964098) Thanks, GBhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1687337/launchxl-f29h85x-f29h850tu-cpu1-stuck-in-boot-rom-nmi-wait-boot-after-secure-entry-error-unable-to-program-flash-via-jtag-pc_force-error/6509272Tue, 13 Oct 2026 15:17:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:7eefa484-e228-4ec7-b59a-22b219cb70fcPrarthan BhattAs I explained there should not be any systematic error that causes NMI error when ROM executes. There can be application errors that are not handled in application NMI can cause ROM NMI ISR entry if not handled by application NMI ISR . The non handling or unexpected entry in ROM NMI ISR should be debugged and the device to be taken offline for debug not just re-programmed without any root cause analysis on production line (ideally). Programming is blocked, if CPU context is in ISR for reasons already explained earlier. If you see any specific test case which proves otherwise we can check that specifically rather than generalizing. [quote userid=&quot;720916&quot; url=&quot;~/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1687337/launchxl-f29h85x-f29h850tu-cpu1-stuck-in-boot-rom-nmi-wait-boot-after-secure-entry-error-unable-to-program-flash-via-jtag-pc_force-error/6507160&quot;] On Rev C, what does BootROM do when the code at 0x10001000 does not contain valid ENTRY1.PROT || ENTRY2.PROT instructions? Does it enter Wait Boot in a non-ISR context, allowing JTAG Flash programming without changing the Flash Boot configuration in SECCFG? [/quote] Yes enters wait boot loop at point where CPU context is not in ISR, so programming can be performed to change the app code. ROM checks for entry prot instruction at code start addr and if it doesnt find these then jump to code start is not performed which prevents the error in first place. In case of unrecoverable errors like ECC error during ROM execution -&gt; refer to section - Exceptions and Interrupts Handling in manual for more details. Thankshttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1689212/tms320f28377d-suspected-part-number-mark-mis-match/6509231Tue, 13 Oct 2026 14:56:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:9bdeaa54-f013-4a00-a9e0-34241e8c2fe2Joseph CasugaHello Hang, In CCS, can you inspect the memory contents of 0x70202 (PARTIDH). 377 part will have 0x00FF0400. 375 part will have 0x00FD0400. Regards, Josephhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1688196/f28377d-sep-license-requirements-for-software-used-with-the-tms320f28377d-sep/6509219Tue, 13 Oct 2026 14:41:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:2908745f-7c4b-458b-bc45-8a989e4fd3cbMatthewPateThanks for the follow up question, all of the above are allowed under the licensing agreement, both distribution of the completed HW product running C2000Ware based FW, as well as compiled FW case you mention. No separate license is required. Best, Matthewhttps://e2e.ti.com/support/microcontrollers/c2000-microcontrollers-group/c2000/f/c2000-microcontrollers-forum/1678705/tms320f28069-why-the-content-of-the-reserved-opt-area-0x3d7bfa-0x3dc00-in-a-virgin-chip-is-not-empty/6509145Tue, 13 Oct 2026 14:00:00 GMTcb01d8b2-d089-468d-babb-77d1d8683490:ebc60e55-702b-4002-aebe-5f69507baa5cArpit VarahmihirHi Urs, Let me look into the issue and get back to you. Regards Arpit