Part Number: TMS320F28075
I am trying to understand why I am getting inconsistent ADC interrupts. The ADC is triggered by a PWM clock and then it interrupts the CPU when the conversions are complete. The interrupt triggers at a rate of 2500Hz, and I am missing every 4th or 5th interrupt in the sequence (I have a GPIO bit toggling high and low for each, so I can see when it does not trigger). I have ruled out other known interrupts, but now am wondering if there are times within the operation of TI-RTOS that could be blocking interrupts for a short time.
I new to TI-RTOS, but understand that when it is running it runs at times in an interrupt context and so would block or at least delay other interrupts. Is there a way to re-enable interrupts from within TI-RTOS so that longer tasks will be interrupted before they are blocked or switched? .... or some other way to allow my ADC interrupt to be triggered more consistently?
In reply to ToddMullanix:
In reply to Aaron Needles:
In reply to Whitney Dewey:
I took another look at your code, and I suspect that burst mode isn't doing what you're expecting it to do. Burst mode walks through BURSTSIZE+1 consecutive SOCs every time a trigger is received. The SOC that the burst converts first is determined by the round-robin pointer--meaning it doesn't start over at SOC0 every time. Since you were doing bursts of 7 and there are 16 SOCs total, your interrupts were inconsistently spaced.
I suspect you should just configure all the TRIGSEL fields of the SOCs you're using to the same source. They'll still convert one after another on a single trigger. Let me know if that gets you what you expected.
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