• Resolved

TMS320F28377S: PWM is blocked when syncin is on

Prodigy 20 points

Replies: 2

Views: 47

Part Number: TMS320F28377S

Hi.

My slave board is based on F28377S and main on F28377D. The main board generates a EXTSYNCOUT signal to syncronise the slave board PWM TBCTR.  The EXTSYNCOUT signal can be capatured by  oscilloscope and can trigger an xint2 interrupt to slave board. But with this EXTSYNCOUT signal connected to slave board, the pwm1 to pwm12 of slave board is blocked. Menawhile, as long as the EXTSYNCOUT signal is disconnected, the pwm1 to 12 is recoverd to square wave. I examined the codes of pwm many times, especially the part of TZ and DC, and find no wrong code. So I need your help to solve this problem. Below is my codes of pwm.

// ****************************************************************************
// ****************************************************************************
// TODO PWM Configuration
// ****************************************************************************
// ****************************************************************************
void PWM_1ch_UpDwnCnt_CNF(int16 n, Uint16 period, int16 db) {

// Time Base SubModule Registers
(*ePWM[n]).TBCTL.bit.PRDLD = TB_SHADOW; // set Immediate load
(*ePWM[n]).TBPRD = period/2 ; // PWM frequency = 1 / period 5000 for 50us
(*ePWM[n]).TBCTR = 0x0000 ;
(*ePWM[n]).TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN;
(*ePWM[n]).TBCTL.bit.HSPCLKDIV = TB_DIV1;
(*ePWM[n]).TBCTL.bit.CLKDIV = TB_DIV1;

if(CONTROLLERID == MAINCON )
{
switch ( n ) {
case 1: (*ePWM[n]).TBCTL.bit.PHSEN = TB_DISABLE; //upper arm
(*ePWM[n]).TBPHS.bit.TBPHS = 0;
(*ePWM[n]).TBCTL.bit.PHSDIR = TB_COUNT_UP;
break;
case 2: (*ePWM[n]).TBCTL.bit.PHSEN = TB_ENABLE;
(*ePWM[n]).TBPHS.bit.TBPHS = 2500;
(*ePWM[n]).TBCTL.bit.PHSDIR = TB_COUNT_DOWN;
break;
case 3: (*ePWM[n]).TBCTL.bit.PHSEN = TB_ENABLE;
(*ePWM[n]).TBPHS.bit.TBPHS = 5000;
(*ePWM[n]).TBCTL.bit.PHSDIR = TB_COUNT_DOWN;
break;
case 4: (*ePWM[n]).TBCTL.bit.PHSEN = TB_ENABLE;
(*ePWM[n]).TBPHS.bit.TBPHS = 2500;
(*ePWM[n]).TBCTL.bit.PHSDIR = TB_COUNT_UP;
break;
case 5: (*ePWM[n]).TBCTL.bit.PHSEN = TB_ENABLE;
(*ePWM[n]).TBPHS.bit.TBPHS = 0x0;
(*ePWM[n]).TBCTL.bit.PHSDIR = TB_ENABLE;
break;
case 6: (*ePWM[n]).TBCTL.bit.PHSEN = TB_ENABLE;
(*ePWM[n]).TBPHS.bit.TBPHS = 0x0;
(*ePWM[n]).TBCTL.bit.PHSDIR = TB_ENABLE;
break;
case 7: (*ePWM[n]).TBCTL.bit.PHSEN = TB_ENABLE; //lower arm
(*ePWM[n]).TBPHS.bit.TBPHS = 0;
(*ePWM[n]).TBCTL.bit.PHSDIR = TB_COUNT_UP;
break;
case 8: (*ePWM[n]).TBCTL.bit.PHSEN = TB_ENABLE;
(*ePWM[n]).TBPHS.bit.TBPHS = 2500;
(*ePWM[n]).TBCTL.bit.PHSDIR = TB_COUNT_DOWN;
break;
case 9: (*ePWM[n]).TBCTL.bit.PHSEN = TB_ENABLE;
(*ePWM[n]).TBPHS.bit.TBPHS = 5000;
(*ePWM[n]).TBCTL.bit.PHSDIR = TB_COUNT_DOWN;
break;
case 10: (*ePWM[n]).TBCTL.bit.PHSEN = TB_ENABLE;
(*ePWM[n]).TBPHS.bit.TBPHS = 2500;
(*ePWM[n]).TBCTL.bit.PHSDIR = TB_COUNT_UP;
break;
case 11: (*ePWM[n]).TBCTL.bit.PHSEN = TB_ENABLE;
(*ePWM[n]).TBPHS.bit.TBPHS = 0x0;
(*ePWM[n]).TBCTL.bit.PHSDIR = TB_ENABLE;
break;
case 12: (*ePWM[n]).TBCTL.bit.PHSEN = TB_ENABLE;
(*ePWM[n]).TBPHS.bit.TBPHS = 0x0;
(*ePWM[n]).TBCTL.bit.PHSDIR = TB_ENABLE;
break;
default:
break;
} // end switch
if( n == 1 )
{
EALLOW;
// OutputXbarRegs.OUTPUT6MUX0TO15CFG.bit.MUX14 = 3; // GPIO29 for EXTSYNCOUT
// OutputXbarRegs.OUTPUT6MUXENABLE.bit.MUX14 = 1 ;
// OutputXbarRegs.OUTPUTLATCH.bit.OUTPUT1 = 1 ;
// OutputXbarRegs.OUTPUTINV.bit.OUTPUT1 = 0 ;
EDIS;
EALLOW;
GPIO_SetupPinMux(6, GPIO_MUX_CPU1, 3); //Master Board Setting
GPIO_SetupPinOptions(6, GPIO_OUTPUT, GPIO_PUSHPULL); //Master Board Setting
EDIS;
(*ePWM[n]).EPWMSYNCOUTEN.bit.ZEROEN = SYNCOUT_ENABLE;
(*ePWM[n]).TBCTL.bit.SYNCOSEL = TB_CTR_ZERO; // sync "down-stream" MAINCON EPWM1 perform (*ePWM[1]).TBCTL.bit.SWFSYNC=1;
// to give a synchronising signal to MAINCON EPWM2-12 and SLAVECON EPWM1-12
EALLOW;
SyncSocRegs.SYNCSELECT.bit.SYNCOUT = EPwm1SyncOut ;
EDIS;
}
else
{
(*ePWM[n]).TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync "sync in"


}

switch ( n ) {

case 4: EALLOW; SyncSocRegs.SYNCSELECT.bit.EPWM4SYNCIN = EPwm1SyncOut; EDIS; break;
case 7: EALLOW; SyncSocRegs.SYNCSELECT.bit.EPWM7SYNCIN = EPwm1SyncOut; EDIS; break;
case 10: EALLOW; SyncSocRegs.SYNCSELECT.bit.EPWM10SYNCIN = EPwm1SyncOut; EDIS; break;
default: break;

}
} // end if-- MAINCON
else if(CONTROLLERID == SLAVECON )
{
switch ( n ) {
case 1: (*ePWM[n]).TBCTL.bit.PHSEN = TB_ENABLE; //upper arm
(*ePWM[n]).TBPHS.bit.TBPHS = 0;
(*ePWM[n]).TBCTL.bit.PHSDIR = TB_COUNT_UP;
break;
case 2: (*ePWM[n]).TBCTL.bit.PHSEN = TB_ENABLE;
(*ePWM[n]).TBPHS.bit.TBPHS = 2500;
(*ePWM[n]).TBCTL.bit.PHSDIR = TB_COUNT_DOWN;
break;
case 3: (*ePWM[n]).TBCTL.bit.PHSEN = TB_ENABLE;
(*ePWM[n]).TBPHS.bit.TBPHS = 5000;
(*ePWM[n]).TBCTL.bit.PHSDIR = TB_COUNT_DOWN;
break;
case 4: (*ePWM[n]).TBCTL.bit.PHSEN = TB_ENABLE;
(*ePWM[n]).TBPHS.bit.TBPHS = 2500;
(*ePWM[n]).TBCTL.bit.PHSDIR = TB_COUNT_UP;
break;
case 5: (*ePWM[n]).TBCTL.bit.PHSEN = TB_ENABLE;
(*ePWM[n]).TBPHS.bit.TBPHS = 0x0;
(*ePWM[n]).TBCTL.bit.PHSDIR = TB_ENABLE;
break;
case 6: (*ePWM[n]).TBCTL.bit.PHSEN = TB_ENABLE;
(*ePWM[n]).TBPHS.bit.TBPHS = 0x0;
(*ePWM[n]).TBCTL.bit.PHSDIR = TB_ENABLE;
break;
case 7: (*ePWM[n]).TBCTL.bit.PHSEN = TB_ENABLE; //lower arm
(*ePWM[n]).TBPHS.bit.TBPHS = 0;
(*ePWM[n]).TBCTL.bit.PHSDIR = TB_COUNT_UP;
break;
case 8: (*ePWM[n]).TBCTL.bit.PHSEN = TB_ENABLE;
(*ePWM[n]).TBPHS.bit.TBPHS = 2500;
(*ePWM[n]).TBCTL.bit.PHSDIR = TB_COUNT_DOWN;
break;
case 9: (*ePWM[n]).TBCTL.bit.PHSEN = TB_ENABLE;
(*ePWM[n]).TBPHS.bit.TBPHS = 5000;
(*ePWM[n]).TBCTL.bit.PHSDIR = TB_COUNT_DOWN;
break;
case 10: (*ePWM[n]).TBCTL.bit.PHSEN = TB_ENABLE;
(*ePWM[n]).TBPHS.bit.TBPHS = 2500;
(*ePWM[n]).TBCTL.bit.PHSDIR = TB_COUNT_UP;
break;
case 11: (*ePWM[n]).TBCTL.bit.PHSEN = TB_ENABLE;
(*ePWM[n]).TBPHS.bit.TBPHS = 0x0;
(*ePWM[n]).TBCTL.bit.PHSDIR = TB_ENABLE;
break;
case 12: (*ePWM[n]).TBCTL.bit.PHSEN = TB_ENABLE;
(*ePWM[n]).TBPHS.bit.TBPHS = 0x0;
(*ePWM[n]).TBCTL.bit.PHSDIR = TB_ENABLE;
break;
default:
break;
} // end switch

if ( n == 1 )
{

EALLOW;
InputXbarRegs.INPUT5SELECT = 99; //Slave Board Setting
EDIS;

EALLOW;
GPIO_SetupPinMux(99, GPIO_MUX_CPU1, 0); //Slave Board Setting
GPIO_SetupPinOptions(99, GPIO_INPUT, GPIO_ASYNC); //Slave Board Setting
// GPIO_SetupPinOptions(99, GPIO_OUTPUT, GPIO_PUSHPULL); //Slave Board Setting for test
EDIS;


XintRegs.XINT2CR.bit.ENABLE = 1 ; //Interrupt Enabled
XintRegs.XINT2CR.bit.POLARITY = 1 ; //Interrupt is selected as positive edge triggered
}
switch ( n ) {

case 4: EALLOW; SyncSocRegs.SYNCSELECT.bit.EPWM4SYNCIN = EPwm1SyncOut; EDIS; break;
case 7: EALLOW; SyncSocRegs.SYNCSELECT.bit.EPWM7SYNCIN = EPwm1SyncOut; EDIS; break;
case 10: EALLOW; SyncSocRegs.SYNCSELECT.bit.EPWM10SYNCIN = EPwm1SyncOut; EDIS; break;
default: break;

}

(*ePWM[n]).TBCTL.bit.SYNCOSEL = TB_SYNC_IN; // sync "down-stream"
} //end else if--SLAVECON


// Counter Compare Submodule Registers
(*ePWM[n]).CMPCTL.bit.SHDWAMODE = CC_SHADOW;
(*ePWM[n]).CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
(*ePWM[n]).CMPCTL.bit.LOADASYNC = CC_LDMODE;
(*ePWM[n]).CMPCTL.bit.SHDWBMODE = CC_SHADOW;
(*ePWM[n]).CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
(*ePWM[n]).CMPCTL.bit.LOADBSYNC = CC_LDMODE;


// Action Qualifier SubModule Registers
(*ePWM[n]).AQCTL.bit.SHDWAQAMODE =AQ_SHDWAQ_IMME;
(*ePWM[n]).AQCTL.bit.SHDWAQBMODE =AQ_SHDWAQ_IMME;
(*ePWM[n]).AQCTL.bit.LDAQAMODE =AQ_LDAQ_ZRO;
(*ePWM[n]).AQCTL.bit.LDAQBMODE =AQ_LDAQ_ZRO;
(*ePWM[n]).AQCTLA.bit.CAU = AQ_CLEAR;
(*ePWM[n]).AQCTLA.bit.CAD = AQ_SET;
(*ePWM[n]).AQCTLB.bit.CBU = AQ_SET;
(*ePWM[n]).AQCTLB.bit.CBD = AQ_CLEAR;

// Active high complementary PWMs - Set up the deadband
/* (*ePWM[n]).DBCTL.bit.IN_MODE = DBA_ALL; */
(*ePWM[n]).DBCTL.bit.OUT_MODE = DB_DISABLE;
(*ePWM[n]).DBCTL.bit.OUTSWAP = DB_DISABLE;
/* (*ePWM[n]).DBCTL.bit.POLSEL = DB_ACTV_HIC;
(*ePWM[n]).DBRED = db;
(*ePWM[n]).DBFED = db;
*/

// Trip Zone Submodule Registers
EALLOW;
// InputXbarRegs.INPUT1SELECT = 0x43; //GPIO67 for fault input in maincon active low
EDIS;
EALLOW;
// (*ePWM[n]).TZSEL.bit.CBC1 = TZ_ENABLE;
// (*ePWM[n]).TZCTL.bit.TZA = TZ_FORCE_LO;
// (*ePWM[n]).TZCTL.bit.TZB = TZ_FORCE_LO;
(*ePWM[n]).TZCBCCLR.bit.CBC1 = TZ_ENABLE;
(*ePWM[n]).TZCLR.bit.CBC = TZ_ENABLE; //for test
(*ePWM[n]).TZCLR.bit.INT = TZ_ENABLE; //for test
(*ePWM[n]).TZEINT.bit.CBC = TZ_ENABLE;
EDIS;

// Event Trigger Submodule Registers
if( n == 1 )
{
(*ePWM[n]).ETSEL.bit.INTSEL = ET_CTR_ZERO;
(*ePWM[n]).ETSEL.bit.INTEN = ET_ENABLE;
}
(*ePWM[n]).ETSEL.bit.SOCASELCMP = ET_DISABLE;
(*ePWM[n]).ETSEL.bit.SOCBSELCMP = ET_DISABLE;
(*ePWM[n]).ETSEL.bit.INTSELCMP = ET_DISABLE;
(*ePWM[n]).ETSEL.bit.SOCASEL = ET_CTR_ZERO;
(*ePWM[n]).ETSEL.bit.SOCAEN = ET_ENABLE;
(*ePWM[n]).ETSEL.bit.SOCBSEL = ET_CTR_ZERO;
(*ePWM[n]).ETSEL.bit.SOCBEN = ET_ENABLE;
(*ePWM[n]).ETPS.bit.INTPRD = ET_1ST;
(*ePWM[n]).ETPS.bit.INTPSSEL = 0x0; //0x0 : action as ETPS,0x1: action as ETINTPS
(*ePWM[n]).ETPS.bit.SOCPSSEL = 0x0; //0x0 : action as ETPS,0x1: action as ETSOCPS
(*ePWM[n]).ETPS.bit.SOCAPRD = ET_1ST;
(*ePWM[n]).ETPS.bit.SOCBPRD = ET_1ST;

}

ISR:

__interrupt void epwm1_isr(void)
{
//
// Update the CMPA and CMPB values
//
Uint16 n;

for( n=1; n< (NumModular+4+1) ; n++) {
thetaa[n] = (TWO_PI*indexa[n])/20000 + faia ; // calculate ref angle
indexa[n] +=50 ; // update ref angle for next cycle

switch (n) {
case 1 : if(indexa[1] > 20000 ) { indexa[1] = 25; }
break;
case 2 : if(indexa[2] > 20012.5 ) { indexa[2] = 37.5; }
break;
case 3 : if(indexa[3] > 20025 ) { indexa[3] = 50; }
break;
case 4 : if(indexa[4] > 20037.5 ) { indexa[4] = 62.5; }
break;
case 5 : if(indexa[5] > 20000 ) { indexa[5] = 25; }
break;
case 6 : if(indexa[6] > 20000 ) { indexa[6] = 37.5; }
break;
case 7 : if(indexa[7] > 20000 ) { indexa[7] = 50; }
break;
case 8 : if(indexa[8] > 20000 ) { indexa[8] = 62.5; }
break;
case 9 : if(indexa[9] > 20000 ) { indexa[9] = 25; }
break;
case 10 : if(indexa[10] > 20000 ) { indexa[10] = 25; }
break;
case 11 : if(indexa[11] > 20000 ) { indexa[11] = 25; }
break;
case 12 : if(indexa[12] > 20000 ) { indexa[12] = 25; }
break;
default: break;
} //end switch

refaval[n] = Kpwm*( 1+mod_index*cos( thetaa[n] ) )/2 ;
refa[n] = refaval[n] + refadelta[n] ;
refa[n] = INV_PWM_TICKS/2 - refa[n] ;
} // end for

// update epwm1
if( (Uint16)( refa[1] ) < dead_time_count )
{
(*ePWM[1]).CMPA.bit.CMPA = (Uint16)( refa[1] ) ;
(*ePWM[1]).CMPB.bit.CMPB = (Uint16)( refa[1] )-dead_time_count ; //dead_time_count
}
else
{
(*ePWM[1]).CMPA.bit.CMPA = (Uint16)( refa[1] ) ;
(*ePWM[1]).CMPB.bit.CMPB = (Uint16)( refa[1] )-dead_time_count ;
}

// update epwm2
if( (Uint16)( refa[2] ) < dead_time_count )
{
(*ePWM[2]).CMPA.bit.CMPA = (Uint16)( refa[2] ) ; //dead_time_count
(*ePWM[2]).CMPB.bit.CMPB = (Uint16)( refa[2] )-dead_time_count ;
}
else
{
(*ePWM[2]).CMPA.bit.CMPA = (Uint16)( refa[2] ) ;
(*ePWM[2]).CMPB.bit.CMPB = (Uint16)( refa[2] )-dead_time_count ;
}

// update epwm3
if( (Uint16)( refa[3] ) < dead_time_count )
{
(*ePWM[3]).CMPA.bit.CMPA = (Uint16)( refa[3] ) ; //dead_time_count
(*ePWM[3]).CMPB.bit.CMPB = (Uint16)( refa[3] )-dead_time_count ;
}
else
{
(*ePWM[3]).CMPA.bit.CMPA = (Uint16)( refa[3] ) ;
(*ePWM[3]).CMPB.bit.CMPB = (Uint16)( refa[3] )-dead_time_count ;
}

// update epwm4
if( (Uint16)( refa[4] ) < dead_time_count )
{
(*ePWM[4]).CMPA.bit.CMPA = (Uint16)( refa[4] ) ; //dead_time_count
(*ePWM[4]).CMPB.bit.CMPB = (Uint16)( refa[4] )-dead_time_count ;
}
else
{
(*ePWM[4]).CMPA.bit.CMPA = (Uint16)( refa[4] ) ;
(*ePWM[4]).CMPB.bit.CMPB = (Uint16)( refa[4] )-dead_time_count ;
}

// update epwm5
if( (Uint16)( refa[5] ) < dead_time_count )
{
(*ePWM[5]).CMPA.bit.CMPA = (Uint16)( refa[5] ) ; //dead_time_count
(*ePWM[5]).CMPB.bit.CMPB = (Uint16)( refa[5] )-dead_time_count ;
}
else
{
(*ePWM[5]).CMPA.bit.CMPA = (Uint16)( refa[5] ) ;
(*ePWM[5]).CMPB.bit.CMPB = (Uint16)( refa[5] )-dead_time_count ;
}

// update epwm6
if( (Uint16)( refa[6] ) < dead_time_count )
{
(*ePWM[6]).CMPA.bit.CMPA = (Uint16)( refa[6] ) ; //dead_time_count
(*ePWM[6]).CMPB.bit.CMPB = (Uint16)( refa[6] )-dead_time_count ;
}
else
{
(*ePWM[6]).CMPA.bit.CMPA = (Uint16)( refa[6] ) ;
(*ePWM[6]).CMPB.bit.CMPB = (Uint16)( refa[6] )-dead_time_count ;
}

// update epwm7
if( (Uint16)( refa[7] ) < dead_time_count )
{
(*ePWM[7]).CMPA.bit.CMPA = (Uint16)( refa[7] ) ; //dead_time_count
(*ePWM[7]).CMPB.bit.CMPB = (Uint16)( refa[7] )-dead_time_count ;
}
else
{
(*ePWM[7]).CMPA.bit.CMPA = (Uint16)( refa[7] ) ;
(*ePWM[7]).CMPB.bit.CMPB = (Uint16)( refa[7] )-dead_time_count ;
}

// update epwm8
if( (Uint16)( refa[8] ) < dead_time_count )
{
(*ePWM[8]).CMPA.bit.CMPA = (Uint16)( refa[8] ) ; //dead_time_count
(*ePWM[8]).CMPB.bit.CMPB = (Uint16)( refa[8] )-dead_time_count ;
}
else
{
(*ePWM[8]).CMPA.bit.CMPA = (Uint16)( refa[8] ) ;
(*ePWM[8]).CMPB.bit.CMPB = (Uint16)( refa[8] )-dead_time_count ;
}

// update epwm9
if( (Uint16)( refa[9] ) < dead_time_count )
{
(*ePWM[9]).CMPA.bit.CMPA = (Uint16)( refa[9] ) ; //dead_time_count
(*ePWM[9]).CMPB.bit.CMPB = (Uint16)( refa[9] )-dead_time_count ;
}
else
{
(*ePWM[9]).CMPA.bit.CMPA = (Uint16)( refa[9] ) ;
(*ePWM[9]).CMPB.bit.CMPB = (Uint16)( refa[9] )-dead_time_count ;
}

// update epwm10
if( (Uint16)( refa[10] ) < dead_time_count )
{
(*ePWM[10]).CMPA.bit.CMPA = (Uint16)( refa[10] ) ; //dead_time_count
(*ePWM[10]).CMPB.bit.CMPB = (Uint16)( refa[10] )-dead_time_count ;
}
else
{
(*ePWM[10]).CMPA.bit.CMPA = (Uint16)( refa[10] ) ;
(*ePWM[10]).CMPB.bit.CMPB = (Uint16)( refa[10] )-dead_time_count ;
}

// update epwm11
if( (Uint16)( refa[11] ) < dead_time_count )
{
(*ePWM[11]).CMPA.bit.CMPA = (Uint16)( refa[11] ) ; //dead_time_count
(*ePWM[11]).CMPB.bit.CMPB = (Uint16)( refa[11] )-dead_time_count ;
}
else
{
(*ePWM[11]).CMPA.bit.CMPA = (Uint16)( refa[11] ) ;
(*ePWM[11]).CMPB.bit.CMPB = (Uint16)( refa[11] )-dead_time_count ;
}

// update epwm12
if( (Uint16)( refa[12] ) < dead_time_count )
{
(*ePWM[12]).CMPA.bit.CMPA = (Uint16)( refa[12] ) ; //dead_time_count
(*ePWM[12]).CMPB.bit.CMPB = (Uint16)( refa[12] )-dead_time_count ;
}
else
{
(*ePWM[12]).CMPA.bit.CMPA = (Uint16)( refa[12] ) ;
(*ePWM[12]).CMPB.bit.CMPB = (Uint16)( refa[12] )-dead_time_count ;
}

if( count < 400 ){
carrier1[count ] = refa[1] ;
carrierint1[count ] = GpioDataRegs.GPBDAT.bit.GPIO37 ; //ePWM[1]->CMPA.bit.CMPA ; //refa[1] ;
carrier2[count ] = refa[2] ;
carrierint2[count ] = ePWM[2]->TBCTR ;
carrier3[count ] = refa[3] ;
carrierint3[count ] = ePWM[3]->TBCTR ;
carrier4[count ] = refa[4] ;
carrierint4[count++ ] = ePWM[4]->TBCTR ;
}
else
{
count = 0 ;
carrier1[count ] = refa[1] ;
carrierint1[count ] = GpioDataRegs.GPBDAT.bit.GPIO37 ;
carrier2[count ] = refa[2] ;
carrierint2[count ] = refa[2] ;
carrier3[count ] = refa[3] ;
carrierint3[count ] = refa[3] ;
carrier4[count ] = refa[4] ;
carrierint4[count ] = refa[4] ;
count++ ;
}

//Generate carriers
// phasecarriergen( Initcarrierphasea, carriera, directionupa );
// phasecarriergen( Initcarrierphaseb, carrierb, directionupb );
// phasecarriergen( Initcarrierphasec, carrierc, directionupc );

//
// Clear INT flag for this timer
//
EPwm1Regs.ETCLR.bit.INT = 1;

//
// Acknowledge this interrupt to receive more interrupts from group 3
//
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}

XINT2:

// 1.5 - XINT2 Interrupt
__interrupt void xint2_isr(void)
{
// Insert ISR Code here

XINT2CTR[icount++] = XintRegs.XINT2CTR ;
if(icount == 400) icount=0;
// GpioDataRegs.GPBTOGGLE.bit.GPIO56 = 1;

// To receive more interrupts from this PIE group,
// acknowledge this interrupt.
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;


// Next two lines for debug only to halt the processor here
// Remove after inserting ISR Code
// asm (" ESTOP0");
// for(;;);
}

  

  • The extsyncout signal should be one pulse. Is that not the case?

  • In reply to Nima Eskandari:

    Yes,extsyncout signal is a pulse. Eventually, syncin signal should be qualified to filter noise so that the pwm could not be triggerd by noise. Thanks a lot.