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TMS320F2803X Piccolo ePWM Module for 0% and 100% Duty Cycle Control

Other Parts Discussed in Thread: CONTROLSUITE

Hello,

Is there any possibility to control the duty cycle at 0% and 100%  without using the ISR's?

Seems like it's possible according to the document:

 TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM)          SPRUGE9E–December 2008–Revised March 2011 Page 44.
2.4.4       Waveforms for Common Configurations

........

Figure 23 shows how a symmetric PWM waveform can be generated using the up-down-count mode of
the TBCTR. In this mode 0%-100% DC modulation is achieved by using equal compare matches on the
up count and down count portions of the waveform. In the example shown, CMPA is used to make the
comparison. When the counter is incrementing the CMPA match will pull the PWM output high. Likewise,
when the counter is decrementing the compare match will pull the PWM signal low. When CMPA = 0, the
PWM signal is low for the entire period giving the 0% duty waveform. When CMPA = TBPRD, the PWM
signal is high achieving 100% duty.
When using this configuration in practice, if you load CMPA/CMPB on zero, then use CMPA/CMPB values
greater than or equal to 1. If you load CMPA/CMPB on period, then use CMPA/CMPB values less than or
equal to TBPRD-1. This means there will always be a pulse of at least one TBCLK cycle in a PWM period
which, when very short, tend to be ignored by the system.....

but there is another document where it's stated that ISR's are required for it:

Application Report
SPRAAI1–December 2006

Using the Enhanced Pulse Width Modulator (ePWM)
Module for 0% to 100% Duty Cycle Control

I just need to drive some independent PWM outputs(Full range including 0% & 100%), symmetric or asymmetric and without Dead-Band or PWM-Chopper

Thanks,

  • Hi Henry

    Of course you can generate PWM without ISR's. The need for ISR's is usually defined by the system architecture - i.E. do you have a lot of other tasks to be served, is your PWM generation part of a time critical control loop, is there a need of priority scheduling....
    But for simple PWM generation you can directly write into the respective registers. I suppose you to have a look into the examples provided with controlSUITE, there you can learn a lot about PWM generation!

    Best regards

    Andreas

  • I have been testing some configurations to generate a single PWM signal, but I have a problem when loading the CMPA value greater than the TBPRD value for the following configuration:

    - Up-Down counter
    - CMPA load on TBCTR = 0x0000
    - CAD Force output LOW ( CMPA == TBCTR and Counter Decrementing)
    - CAU Force output HI  ( CMPA == TBCTR and Counter Incrementing)
    - CMPA register in shadow mode
    - DeadBand disabled
    - Forcing actions disabled
    - TZ and DC compare actions disabled
    - Chopper Disabled

    During initialization the CMPA and TBCTR values are initialized to 0, so as soon as the module is activated the CAU Force output HI condition is met and the pin goes HI as expected.

    After the initialization, for any value between 0 and PWM_PERIOD loaded into the CMPA, the PWM works as expected.

    The situation that is not clear for me is when a value > PWM_PERIOD is loaded into CMPA:

    i.e:

    - At Initialization : TBPRD = PWM_PERIOD, CMPA = 0.
    The output remains HI as expected, as the only condition being triggered is : CAU Force output HI (CMPA == TBCTR and Counter Incrementing)

    if after Initialization CPMA is loaded with a value > PWM_PERIOD(I update the new value after 50ms) , lets say 11000, then the output signal goes LOW.
    From my point of view it should not go LOW, as the only active  condition to force the output LOW is CAD ( CMPA == TBCTR and Counter Decrementing), and it's supossed that the TBCTR never reaches the CMPA value and the condition CMPA = TBCTR is not present according to:

    SPRUGE9E–December 2008–Revised March 2011 TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) Module PAGE 44.

    Table 12. Behavior if CMPA/CMPB is Greater than the Period


    Probably I'm not understanding the datasheet or maybe there is a mistake on my Initialization process.
    Could anybody please help me to understand what is the problem?


    Here is my Initialization process:

    #define PWM_PERIOD          10000U

    Initialization:

    void PWM_Init(void)
    {
    EALLOW;
    SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;
    EDIS;

    EPwm1Regs.TBCTL.bit.CTRMODE = 0x3;        // Disable the timer

    EPwm1Regs.TBCTL.all = 0x0033;        // Sync Out Disabled, Disable the timer

    EPwm1Regs.TBCTR = 0U;
    EPwm1Regs.TBPRD = PWM_PERIOD;        // Set timer period
    EPwm1Regs.TBPHS.half.TBPHS = 0x0000;    // Set timer phase

    EPwm1Regs.CMPA.half.CMPA = 0U;        // Set PWM duty cycle
       
    EPwm1Regs.CMPCTL.all = 0x0000;        // Shadow mode, load on zero match

    EPwm1Regs.AQCTLA.all = 0x0060;        // Action-qualifier control register A
    // bit 15-12     0000:   reserved
    // bit 11-10     00:     CBD, 00 = do nothing
    // bit 9-8       00:     CBU, 00 = do nothing
    // bit 7-6       01:     CAD, 01 = clear       <---------
    // bit 5-4       10:     CAU, 10 = set         <---------
    // bit 3-2       00:     PRD, 00 = do nothing
    // bit 1-0       00:     ZRO, 00 = do nothing


    EPwm1Regs.AQSFRC.all = 0x0000;        // forcing disabled register

    EPwm1Regs.AQCSFRC.all = 0x0000;        // forcing disabled register

    EPwm1Regs.DBCTL.all = 0;            // Deadband disabled   
    EPwm1Regs.DBRED = 0;
    EPwm1Regs.DBFED = 0;   
       
    EPwm1Regs.PCCTL.bit.CHPEN = 0;        // PWM chopper unit disabled
    EPwm1Regs.TZDCSEL.all = 0x0000;        // TZ and DC compare actions disabled

    EPwm1Regs.TBCTL.bit.CTRMODE = 0x2;        // Enable the timer in count up/down mode


    EALLOW;
    SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1U;    // TBCLK to ePWM modules enabled
    EDIS;
    }



    Then after 50ms I just update the CMPA register like this:

    EPwm1Regs.CMPA.half.CMPA = 11000;

    Thanks,

  • Hi Henry,

    Henry Abril said:
    Probably I'm not understanding the datasheet

    I think that is the case... in table 12 it is written, that the event will occur if TBCTR = TBPRD. So the LOW transition is valid.

    Best regards

    Andreas

  • Hi Andreas,

     

    Thanks for your support.  Yes, I was misunderstanding the datasheet.

    Anyway on the second column of the Table 12. Behavior if CMPA/CMPB is Greater than the Period it should be:

    Compare on Up-Count Event
    CAU/CBU

    Instead of:

    Compare on Up-Count Event
    CAD/CBD

    Right?

    Best Regards,

  • Henry Abril said:

    Anyway on the second column of the Table 12. Behavior if CMPA/CMPB is Greater than the Period it should be:

    Compare on Up-Count Event
    CAU/CBU

    Yes that is a mistake in the Document!

    Regards

    Andreas