F28335 - Interrupt an ISR

Chris,

if I understood your question correctly than the answer would be that you need to perform context switching to enable ISRs to interrupt each other. That means storing shared registers and memory locations on start of ISR and restoring them before returning from ISR. See "3.4 Standard Operation for Maskable Interrupts" in document number SPRU430D.

Regards, Josip

Thanks for reply Josip.

I just want to know what happens if an interrupt with higher priority occur, while the ISR from an interrupt with lower priority is serverd.

With best regards,

Chris

Chris,

as explained in the document I mentioned (I strongly recommend reading sect. 3.4), some of the context is automatically stored/restored while servicing an ISR. So if no resource conflixcs exist between your ISRs, besides concerning the part of automatically stored context, no errors should occur. If, on the other hand, more of your ISRs use the same registers/locations that are not stored as a part of the context, there will be trouble. These errors can have the strangest symptoms and are sporadic so they are a pain to debug.

Hope I helped,

Josip

Hi Chris,

To be a bit more specific: Interrupt nesting is not enabled by default on C2000 cores. You need to do this by including special pieces of Code (DSP2802x_SWPrioritizedDefaultIsr.c / DSP2802x_SWPrioritizedPieVect.c / DSP2802x_SWPrioritizedIsrLevels.h) These Files will allow interrupt nesting if properly used.
By writing the word interrupt in front of an interrupt service routine, the compiler adds automatic code to save the context and to disable further interrupt. If you service an interrupt and you don't want it to be interrupted by another - higher priority or not - interrupt, you must not re-enable the interrupts within the interrupt service routine, and you will be safe!

Hope this helps

Best regards Andreas

Chris M. said:

I have several ISRs, and I don't want that an interrupt with a higher priority disrupt the execution of an actual ISR.

So the question is, must I disable the global interrupt?

Upon entering the flow chart mentioned before depicted in Figure 3-4 of the SPRU430 document, the default behavior of the CPU is to set the INTM (interrupt mask) global bit when the CPU takes an interrupt trap initially.  As described in step 11 on page 94 of the stated document, setting INTM=1 prevents maskable interrupts from disturbing the current ISR (my note: even higher priority interrupts).