Concerto M3 can use adc ?

??? The f28m35x specification states:

2.5.4 Analog Common Interface Bus (ACIB)

The ACIB bus links the Master and Control Subsystems with the Analog Subsystem. It enables the

Cortex

™-M3 CPU/μDMA and C28x CPU/DMA to access Analog Subsystem registers, to send SOC

Triggers to the Analog Subsystem, and to receive EOC Interrupts from the Analog Subsystem. The

Cortex

™-M3 uses its System Bus and the μDMA Bus to read from and write to Analog Subsystem

registers. The C28x uses its Memory Bus and the DMA bus to access the same Analog Subsystem

registers. The ACIB arbitrates between up to four possibly simultaneously occurring bus cycles on the

Master/Control Subsystem side of ACIB to access the ADC and Analog Comparator registers on the

Analog Subsystem side.

Does this not imply that the M3 can control the Analog subsystem through the ACIB??

So I pose the same question : are there any examples of how to interact with the Analog subsystem using the M3?

Thanks

Pat

Pat,

The datasheet is in error and needs to be fixed.

The M3 core can only access the ADC result registers.  The M3 uDMA cannot access any ADC registers or result registers.  The M3 system also cannot trigger ADC conversions or receive any EOC interrupts.

The C28x core has access to all ADC registers and results.  This core can trigger conversions and receive EOC interrupts.

Regards,

Ricky

Pat,

One correction, the M3 uDMA can access the ADC result registers.  Sorry for the confusion.

Ricky

OK, thanks. Do you have an example of how to access the result registers from the M3 side?

Pat

The ADC1 result register is accessible by reading the locations 0x50001600 - 0x5000160F and the ADC2 result register is accessible by reading the locations 0x50001680 - 0x5000168F.

Ricky

If I read it on the Master side, how will in coordinate with the interrupt service on the Control side? Is it best to read on the Control side and then transfer the result to the Master side for processing / output? What procedure do you recommend to transfer the analog data? the IPC?

Is there any problem with all of the GPIO being read on the Master side as well? I am also  having problems with this. See post:

http://e2e.ti.com/support/microcontrollers/tms320c2000_32-bit_real-time_mcus/f/171/p/195510/698812.aspx#698812

Thanks,

Pat

I also notice that in your include file hw.memmap.h ADC1 is defined as 0x50001600, and ADC2 is defined as 0x50001640. Is this file for a different processor or a typo?

Pat

Pat,

I am very sorry for the confusion with the interrupts.  I guess Friday was not my day.  The M3 can in fact receive interrupts from the ACIB, so you do not have to worry about coordination or transferring data.

To the other issue, there should not be a problem with using the M3 GPIO.  Comment out this statement for now GPIODirModeSet() for Port G and just execute the following code.  This should definitely toggle the GPIOs on Port G.

GPIOPinTypeGPIOOutput(GPIO_PORTG_BASE, 0xFF);

GPIOPinWrite(GPIO_PORTG_BASE, GPIO_PIN_0, 0x1); 

.... for the other pins changing the middle variable of the function.

GPIOPinWrite(GPIO_PORTG_BASE, GPIO_PIN_0, 0x0);

..... for the other pins changing the middle variable of the function. 

For the third post, v130 of the F28M35x header files should have this updated.

Regards,

RIcky

Pat,

Another correction, for accessing the ADC results using the M3 subsystem the range is 0x50001600 - 0x5000161F and 0x50001680 - 0x5000169F. 

Ricky

Ricky,

So, I do have full control of the analog ports thru the CM3 side, then?

Pat

Pat,

No, you do not have full control on the CM3 side.  All configurations for the ADC must be done by the C28x core.  The Master can read the ADC result registers using the M3 core or the uDMA and receive interrupts from the ADC.  That is all.

Ricky

Ricky,

Is it OK to upgrade the driverlib from v110 to v130 with CCS v4.5? What is the best way to do that, just copy the v130 files into my mware\driverlib folder?

Thanks,

Pat