TMS320F28030 ADC Clock

Hi Suttichai-

The maximum ADC clock is 60Mhz, but the minimum ACQPS for 28030 is 23 ( 24 ADC clock cycles ).  ADC conversion time is 13 cycles, seven of which overlap with the S/H in normal OVERLAP mode.  That leaves six cycles which are not overlapped, so the minimum sample/conversion time for 28030 is 24+6=30 cycles.  At 60Mhz this is 500ns.

best regards,

Joe