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F28M35 - EPI Bus data pin behavior questions

Bas van de Ven
Prodigy 140 points


Hi,

For our application we would like to use the EPI bus configured in General Purpose mode for the communication between the F28M35 Concerto and an external FPGA. However, in order to make sure the peripheral works correctly in our application I would like to know the following:

-What is the drive strength of the EPI data pins? The only thing I could find about this is in the SPRS742C datasheet section 4.2: the ouput current for all GPIO pins is 4 mA, except a few pins in Group 2 which are 8 mA (and those are not part of the EPI pins). However, I noticed that in the technical reference (SPRUH22B) section 19.6.1. that the EPI signals must use 8 mA drive when interfacing to SDRAM. Does this mean the F28M35 cannot interface with SDRAM, or is there some other configuration that I've missed?

-Are the EPI data pins always in a well-defined tristate, when the F28M35 is not actively busy with a write transfer? According to some of the timing diagrams in SPRUH22B they are drawn as tristate (e.g. Figure 19-14), but this is never explicitely mentioned in the technical reference manual nor in the device datasheet (SPRS742C). Can someone shed some light on this?

Thanking in advance,

Bas

  • 0
    TI__Guru** 115881 points

     

    Hi Bas,

    Drive strength of the EPI data pins on F28M35 device is 4mA, as mentioned in the datasheet, and it can interface with the SDRAM.

    There seems to be some mistake in the technical reference manual in this case. We'll correct the same.

    On your other query, related to state of EPI data pin, I'll get back to you in couple of days.

    Regards,


    Vivek Singh

  • 0 in reply to Vivek Singh
    Prodigy 140 points

    Hi Vivek,

    Thanks for the information! This also makes the second part even more important, because with the 4mA it will require us to place a bidirectional driver on the data pins in order to ensure signal integrity. We are thinking of using the EPI WR pin to control the direction of the driver, but then it must be assured that the data isn't driven by the DSP when no write transfer is busy.

    Regards,

    Bas

  • 0 in reply to Bas van de Ven
    TI__Guru** 115881 points

    Hi Bas,

    Data pins will be tri stated when not used. These are driven when there is a WR access, as per the figure shown in the user guide.

    Let me know if you have any further query in this regard.

    Regards,

    Vivek Singh

  • 0 in reply to Vivek Singh
    Prodigy 140 points

    Hello Vivek,

    Thanks for completing the answer of my query; the pin behaviour is now clear to me.

    Regards,

    Bas