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Concerto F28M35 clocking

Other Parts Discussed in Thread: CONTROLSUITE

Hi!

I have a problem with PLL's on Concerto: it doesn't work at 150 MHz (C28) / 75 MHz (M3) - after M3 is starting C28, M3 stop working (permanently rebooting), but c28 is working normal. If set 120 / 60 MHz - both of cores is working normal. How can I fix it?

Thank you! 

  • Hi,

    are you using driver lib API to configure PLL and other dividers?

    Best Regards

    Santosh

  • Hello, Santosh! 

    Yes, we using driver lib API.

    for quartz 20 MHz:

    SysCtlClockConfigSet(SYSCTL_SYSDIV_1 | SYSCTL_M3SSDIV_2 | SYSCTL_USE_PLL | (SYSCTL_SPLLIMULT_M & 0x0F));

    (we was trying also with quartz 8 Mhz)  

    Best Regards

    Alexey

  • Alexey,

    looks good, Master subsystem is verified to work at up to 100 MHz and M3 at 75 MHz and c28x at 150 MHZ is a valid operating range.

    Can you step through the driver lib call and make sure the dividers are being set as expected in your code? Can you check if the below configuration is working?

    // Sets up PLL, M3 running at 100MHz and C28 running at 100MHz

    SysCtlClockConfigSet(SYSCTL_USE_PLL | (SYSCTL_SPLLIMULT_M & 0xA) |SYSCTL_SYSDIV_1 | SYSCTL_M3SSDIV_1 |SYSCTL_XCLKDIV_4);

    Also when you say M3 is rebooting, can you find out why? or what is it trying to execute when it is failing? is it decoding an opcode incorrectly or some peripheral/memory writes are mis behaving? and what is your application trying to do (just to understand the scenario better)?

    Best Regards

    Santosh

  • Santosh,
    we trying to run TI example for Concerto "blinky" from controlsuite. 100/100 MHz is not working. M3 (and now I think C28 too) is failing, when C28 trying to execute InitSysCtrl() (at first row (**InitAnalogSystemClock)(ACLKDIV4); ) When we do not initializing and starting analog subsystem, Concerto run normally at 150/75 MHz. But we need to use ADC etc. at our project... And this fail is unstable: once run at 120/60 Mhz, then maximum at 50/25 MHz... But if not turned on analog subsystem - stable normally.

     Best Regards, Alexey.

  • Alexey,

    Can you try running the exact code in the blinky project. 

    This line is changed "SysCtlClockConfigSet(SYSCTL_SYSDIV_1 | SYSCTL_M3SSDIV_2 | SYSCTL_USE_PLL | (SYSCTL_SPLLIMULT_M & 0x0F));" from what is in our blinky example.  Please let me know if you are able to run this example.

    It should work or there is a problem with the device, which could happen as the F28M35x units are TMX only units.  Are you running this on a controlCARD?

    Regards,

    Ricky

  • We find the answer: at our board to pins 1 and 108 (1.8-V Digital Logic Power Pins (associated with the Analog Subsystem)) was connected capacitors 0.1 uF, but in datasheet they must be more, then 1.2 uF. With 2 uF - All works properly!


    Thanks to all, and i'm sorry :)