Nested interrupt

Hello

I am not sure what you meant by Timer3 interrupt are executed within Timer1 ISR - if you already have two timers running independently then  is it not possible to configure for separate interrupts from Timer 1 and Timer 2? If Timer 2 is running faster than you will have Timer2 ISR executed more numer of times than Timer 1 ISR.

Another approach could be to generate only Timer 2 interrupt (which is running every 2uS) and after every 6 Timer 2 interrupts (12uS) you execute Timer 1 ISR code as well. In this way you will not need to generate two interrupts and your code flow will be simpler.

Actually I am using Timer 1 and Timer 3, I am configuring Timer 3 as 2us and Timer 1 as100 us. Then using Timer 1 Automatic ADC start of conversion takes place for every Timer 1 period match, and then an interrupt is generated at every ADC End of conversion (EOC). So each and every 2us An EOC interrupt is generated. Also I am generating one more interrupt for every Timer 3 period match.

I have two Calculations:

1. One calculation takes around 12us; I need to implement the same calculation within Timer 3 period match ISR

2. Another actual calculation takes around 1.5us; I need to implement the same calculation within ADC ISR

Actually it should perform the following way (My Objective):

If I am doing the same 12us calculation within the Timer 3 ISR, it takes 48us for actual 12us calculation, it is because of the ADC interrupt is generated for every 2 us. Here it is doing 1.5us calculation, then remaining 0.5us CPU is going to perform the Timer 3 ISR. You see the bellow timing diagram.

 I have the following problem:

Suppose the Now CPU is doing within the Timer 3 ISR, An ADC interrupt is generated after completion of the 12us calculation. you could see the bellow timing tiagram. So it is not satisfing my objective. How can Generate an ADC EOC interrupt in-between the timer 3 ISR calculation? So how can do it? can i send you my program?

Timer 3 ISR

____________________________                                                                                                          _______________________                                                                                

|                                                                 |                    ......................                                                              |     

|                                                                 |________                        _________ _________________|                                                                                         

ß----12us calculation in timer 1---à

ß---------                 Each and every 100us the timer 3 ISR is executed               -------------------->

ADC EOC ISR

                                                                 ____________     ____________      ___________    ____

                                                                 |                           |    |                           |    |                         |    |        Goes to timer 3 ISR......................

____________________________|                           |__|                          |__|                        |__|

ß---1.5---à

ß-----2us-------à

Timer 3 ISR

___________________________________________________                                                 ______                                     |                                                                                                                           ..................................                         |                          ......................             |

|                                                                                                                                                                                      |___________                      ______|

ß--------------------        Do the same 12us calculation in timer 1, it takes 48us          --------------------à

ß------------------------------------------                      Each and every 100us the timer 3 ISR is executed                          ----------------------------->

ADC EOC ISR

__________       __________       __________       __________                                                                                    __________     __________

|                      |     |                       |     |                        |     |                       |       ................ ............................................              |                       |    |                      |

|                      |__|                       |__ |                        |__|                       |                                                                                  |                       |__|                     |

ß---1.5---à

ß-----2us-------à

Hello - First , I am sorry, unfortunately I don't have time to go through your code.

I am not following your requirements - you mentioned one of the calculations which takes 12uS which has to be started at Timer 3 period match but your Timer 3 has a period of 2uS ! obviously it will not be possible to fit 12uS calculation in a period of 2us and therefore that calculation will have to be spread over multiple cycles.

You also mentioned ADC start happens at Timer 1 period match which is running at 100uS so I am not sure why ADC interrupt will happen every 2uS.

I suggest you draw a flow chart and allocate required time (aaproximate) for each module to identify your bottleneck. In general it is better to reduce the number of interrupts for a simpler system.

Hi Thiru

I think your problem is to nest interrupts. But as far as i know, you can't nest interrupts using tms320. I often tried, but never succeed. I never tried to acknowledge the interrupt directly by entering to the isr, but i think that would not solve your problem.

Suppose the Now CPU is doing within the Timer 3 ISR, An ADC interrupt is generated after completion of the 12us calculation. you could see the bellow timing tiagram. So it is not satisfing my objective. How can Generate an ADC EOC interrupt in-between the timer 3 ISR calculation? So how can do it? can i send you my program?

What you really want is a hard real time ADC.

Try this:

Generate a ADC Interrupt every 2 us. Use this 2us clock as your timer base. Create a global variable such as adc_tic, and count it up in your interrupt routine.

Use this adc_tic in your main program:

for (;;)

if (adc_tic  > = my_timer_value)

{

 ... calculate whatever you want and don't forget to reset your adc_timer

}

interrupt adc_isr()

{

   adc_tic++;

  acknowledget the interrupt...

}

Just set my_timer_value to the next multiple value of 2us higher than the calculation needs plus all the interrupt calculation times. 10 us calculation in main is splittet in about 20 times 0.5 us processing time. So, you can set my_timer_value to 20.

If you do so, the adc is served every 2us and the calculation is interrupted by the adc interrupt. And after each calcluation, the next calculation will start... and so on.

If you really want to use a hispeed adc conversion, you should think about another design of your controller board. We use an fpga to do all the realtime adc stuff. Fpga serves the adc, calculates results, dsp just reads the results. So, the oversampling will be done outside the dsp.

I hope this will save your problem

Eggi [:)]

Interrupts are disabled by default when you enter an ISR.  They can be re-enabled in software in order to nest interrupts.  There is an example of a software prioritization scheme to do this in the C/C++ Header Files and Peripheral Examples for each specific device family. The name of the example is "sw_prioritized_interrupts".

http://focus.ti.com/docs/toolsw/folders/print/sprc097.html

-Lori

Lori,

Does the code actually allow new interrupts to be serviced while in an interrupt? My understanding of your referenced code, namely "sw_prioritized_interrupts", is an example of determining what order interrupts get evaluated if multiple interrupts are in the "interrupt to be serviced queue", but it does not give an example (or state whether it is possible) to actually halt an interrupt that is currently being serviced.

Please help me figure out if I'm missing something.

Thanks,

- Chris

Chris,

the default operating mode of the C28x regarding interrupts is "No - Nested". However, you can overrule this into a "Nested" system by your own code. 

The default no-nested sequence is this:

ISR1:

1. Hardware context save, including INTM and IER

2. Hardware disables INTM and the corresponding IER-bit

3. Your ISR1 code is executed, including ACK of the PIE

4. Hardware context restore, including the status of INTM and IER as they were set upon entry.

A nested  interrupt - system would look like this:

ISR1:

1. Hardware context save, including INTM and IER

2. Hardware disables INTM and the corresponding IER-bit

3. You enable those IER-lines, which you would like to be able to interrupt ISR1, while ISR1 is still running. Also, enable INTM now. Do also a PIE-ACK here, if your higher prioritized INT is within the same PIE group.

4. Execute your ISR1 code here.  If your higher prioritized ISR (which you enabled in step3) is triggered and it's ISR will interrupt the running ISR1 code.

5. Hardware context restore, including the original status of INTM and IER upon entry at step1.

ISR2:

Same sequence as for ISR1. In step 3 you can qualify other interrupt sources to be of higher priority  than ISR2.

Regards

Perfect!

Thanks!!!

- Chris

Thank you very much this is very helpful.

Emmanuel