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TMS320F28335 Watchdog Reset Detection

Bob10478
Prodigy 40 points

Other Parts Discussed in Thread: TMS320F28335, TMS320F2812

Hi

I'm using a TMS320F28335 and need to use the Watchdog Reset flag (SysCtrlRegs.WDCR & 0x0080) to detect if the there was a normal power up or a watchdog reset event. The circuit is built according to TI reference design for this chip. I'm using the TI headers and example c files as a basis.

// on initializing of system before entering 'main':

lastResetWatchdog = 0;

if(SysCtrlRegs.WDCR & 0x0080)
{
            SysCtrlRegs.WDCR |= 0x0080;    // clear watchdog flag
            lastResetWatchdog = 1;

}

I find that if the reset was due to a watchdog reset the WDFLAG flag is always set, however if there was a normal power up event this flag is in a random state. This causes the system to detect a watchdog reset even if it was a normal power up.

Previously I have used the TMS320F2812 chip, but according to the errata it is not able to accurately detect a watchdog reset. The detection is a critical part of the design and thus the system was upgraded to the TMS320F28335 which seems to have no limitations according to the latest errata on the watchdog reset detection.

Could I be missing something? Please assist.

 

  • 0
    TI__Expert 4745 points

     

     

    You are correct !

     

     

     On the 281x devices, this flag is not reliable since the sampling window for the reset line is too

    short.

    On the 2833x/2823x devices, the sampling interval has been increased to allow more time for

    the reset line to go high after a watchdog reset occurs.

     

    Check Section 3.4 carefully in http://focus.ti.com/lit/ug/sprufb0b/sprufb0b.pdf

    Note that the 2833x the WD must be serviced or disabled within 137,072 instructions after reset.

    I will try to poke around for some example C code.

     

  • 0 in reply to DaveB123
    Intellectual 320 points

    Hi,

    I came across your post on Watchdog. I am encoutering some problems with Watch dog in 28335 processor. My objective is to distinguish the resets caused by some external source or internal watch dog reset. As a primilinary step, without simulating any external reset code and after power up. I was checking the register WDCR if the flag WDFLAG is set or not. My observation is the WDKEY and WDCR registers are always set to 0x0004 and I am expecting WDCR register to 0x0084. (WDFLAG = 1).

    As mentioned in your post, "

    Note that the 2833x the WD must be serviced or disabled within 137,072 instructions after reset ".

    How can I know whether the watch dog is serviced or not? Secondly, is there any possibility to check the reset line by any statusbits etc???

     

     

    Below is code snippet to perform the software reset. When it encounters this below code, I see that WDCNTR restarts from zero.

    EALLOW;
    SysCtrlRegs.WDCR   = 0x0094; 
    EDIS;

     

    Regards,

    KK

  • 0 in reply to Kuldeep Kumar Mynampati
    Intellectual 295 points

    Hi, I'm trying to setup the watchdog to reset the DSP (when the counter reaches the maximum value) but I can only find examples with the watchdog configured with the interruption.

    Is there any code example to show how to correctly configure SysCtrlRegs to do this?

    Regards, 

    Jorge